Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. - Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2001)

Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. - Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (ISMVL, 2002)

Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. - Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

VLSI circuit design using an object-oriented framework of evolutionary graph generation system. - Naofumi Homma; Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi 001 (IEEE Congress on Evolutionary Computation, 2003)

Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. - Masanori Natsui; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (PPSN, 2004)

Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. - Masanori Natsui; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (J. Multiple Valued Log. Soft Comput., 2005)

GA-based approach to pitch recognition of musical consonance. - Masanori Natsui; Shunichi Kubo; Yoshiaki Tadokoro (ICINCO-SPSMC, 2006)

Pitch estimation of difficult polyphony sounds overlapping some frequency components. - Yoshiaki Tadokoro; Masanori Natsui; Yasuhiro Seto; Michiru Yamaguchi (ICINCO-SPSMC, 2006)

Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. - Masanori Natsui; Yoshiaki Tadokoro; Naofumi Homma; Takafumi Aoki; Tatsuo Higuchi 001 (IEICE Electron. Express, 2007)

Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure. - Masanori Natsui; Yoshiaki Tadokoro (ICINCO-ICSO, 2008)

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. - Takashi Matsuura; Hirokatsu Shirahama; Masanori Natsui; Takahiro Hanyu (ISMVL, 2009)

Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. - Masanori Natsui; Takashi Arimitsu; Takahiro Hanyu (ISMVL, 2010)

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. - Hirokatsu Shirahama; Takashi Matsuura; Masanori Natsui; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2010)

Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. - Shoun Matsunaga; Akira Katsumata; Masanori Natsui; Takahiro Hanyu (ISMVL, 2011)

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology. - Takayuki Konishi; Kenji Inazu; Jun Gyu Lee 001; Masanori Natsui; Shoichi Masui; Boris Murmann (IEICE Trans. Electron., 2011)

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. - Shoun Matsunaga; Masanori Natsui; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (ASP-DAC, 2012)

Variation-resilient current-mode logic circuit design using MTJ devices. - Youngkeun Kim; Masanori Natsui; Takahiro Hanyu (ISCAS, 2012)

Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. - Masanori Natsui; Takaaki Nagashima; Takahiro Hanyu (ISMVL, 2012)

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. - Daisuke Suzuki; Masanori Natsui; Takahiro Hanyu (MWSCAS, 2012)

Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system. - Masanori Natsui; Takahiro Hanyu (NEWCAS, 2012)

Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. - Masanori Natsui; Takashi Arimitsu; Takahiro Hanyu (J. Multiple Valued Log. Soft Comput., 2012)

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. - Masanori Natsui; Takahiro Hanyu; Noboru Sakimura; Tadahiko Sugibayashi (ISCAS, 2013)

Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. - Masanori Natsui; Kiyohiro Kashiuchi; Takahiro Hanyu (ISMVL, 2013)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. - Masanori Natsui; Takahiro Hanyu (J. Multiple Valued Log. Soft Comput., 2013)

Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. - Masanori Natsui; Takahiro Hanyu (ISMVL, 2014)

Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. - Masanori Natsui; Takahiro Hanyu (NEWCAS, 2014)

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. - Daisuke Suzuki; Noboru Sakimura; Masanori Natsui; Akira Mochizuki; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. - Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Shoun Matsunaga; Masanori Natsui; Akira Mochizuki (DATE, 2015)

Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. - Takeaki Akutsu; Masanori Natsui; Takahiro Hanyu (ISMVL, 2015)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. - Masanori Natsui; Akira Tamakoshi; Akira Mochizuki; Hiroki Koike; Hideo Ohno; Tetsuo Endoh; Takahiro Hanyu (ISCAS, 2016)

Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. - Naoto Sugaya; Masanori Natsui; Takahiro Hanyu (ISMVL, 2016)

A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. - Masanori Natsui; Naoto Sugaya; Takahiro Hanyu (NEWCAS, 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. - Takahiro Hanyu; Daisuke Suzuki; Naoya Onizawa; Masanori Natsui (DATE, 2017)

Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. - Hiroki Suda; Masanori Natsui; Takahiro Hanyu (ISMVL, 2018)

Design of MTJ-Based nonvolatile logic gates for quantized neural networks. - Masanori Natsui; Tomoki Chiba; Takahiro Hanyu (Microelectron. J., 2018)

Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. - Tomoki Chiba; Masanori Natsui; Takahiro Hanyu (ISMVL, 2019)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)

Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. - Keisuke Sakamoto; Masanori Natsui; Takahiro Hanyu (MWSCAS, 2022)

Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. - Ken Asano; Masanori Natsui; Takahiro Hanyu (ICECS, 2023)

High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. - Fangcen Zhong; Masanori Natsui; Takahiro Hanyu (ISCAS, 2023)

Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. - Ken Asano; Masanori Natsui; Takahiro Hanyu (ISMVL, 2023)

Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. - Kaede Sakai; Masanori Natsui; Takahiro Hanyu (MWSCAS, 2023)

Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices. - Fangcen Zhong; Masanori Natsui; Takahiro Hanyu (IJCNN, 2024)

Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic. - Masanori Natsui; Ken Asano; Takahiro Hanyu (ISMVL, 2024)

Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme. - Tomoo Yoshida; Masanori Natsui; Takahiro Hanyu (MWSCAS, 2024)

Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. - Ken Asano; Masanori Natsui; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2024)

Design of a Low-Energy MTJ-Based Nonvolatile Register Based on a Differential Information Storing Scheme. - Tomoo Yoshida; Masanori Natsui; Takahiro Hanyu (ISCAS, 2025)

An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. - Daisuke Suzuki; Akira Tamakoshi; Tomohiro Yoneda; Masanori Natsui; Yasuhiro Takako; Takahiro Hanyu (ISMVL, 2025)

Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. - Tomohiro Yoneda; Yasuhiro Takako; Akira Tamakoshi; Masanori Natsui; Daisuke Suzuki; Takahiro Hanyu (ISMVL, 2025)

Intelligent Power-Gating Technique with Quick Wake-Up/Sleep Functionality for Spintronics-Based Edge Computing Hardware. - Fangcen Zhong; Masanori Natsui; Takahiro Hanyu (ISMVL, 2025)

Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme. - Masanori Natsui; Takahiro Hanyu (IEEE Access, 2025)