An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). - Yasuhiro Agata; Kenji Motomochi; Yoshifumi Fukushima; Masanori Shirahama; Marefusa Kurumada; Naoki Kuroda; Hiroyuki Sadakata; Kohtaro Hayashi; Toshio Yamada; Kazunari Takahashi; Tsutomu Fujita (IEEE J. Solid State Circuits, 2000)

A 400-MHz random-cycle dual-port interleaved DRAM (D2RAM) with standard CMOS Process. - Masanori Shirahama; Yasuhiro Agata; Toshiaki Kawasaki; Ryuji Nishihara; Wataru Abe; Naoki Kuroda; Hiroyuki Sadakata; Toshitaka Uchikoba; Kazunari Takahashi; Kyoko Egashira; Shinji Honda; Miho Miura; et al. (IEEE J. Solid State Circuits, 2005)

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI. - Yasue Yamamoto; Masanori Shirahama; Toshiaki Kawasaki; Ryuji Nishihara; Shinichi Sumi; Yasuhiro Agata; Hirohito Kikukawa; Hiroyuki Yamauchi (IEICE Trans. Electron., 2007)