A 10-bit 20-MHz two-step parallel A/D converter with internal S/H. - Toshihiko Shimizu; Masao Hotta; Kenji Maio; Seiichi Ueda (IEEE J. Solid State Circuits, 1989)

An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate. - Yoshito Nejime; Masao Hotta; Seiichi Ueda (IEEE J. Solid State Circuits, 1991)

Maximum-likelihood estimation of current-dipole parameters for data obtained using multichannel magnetometer. - Kensuke Sekihara; Yukiko Ogura; Masao Hotta (IEEE Trans. Biomed. Eng., 1992)

Measurement of digital noise in mixed-signal integrated circuits. - Keiko Makie-Fukuda; Takafumi Kikuchi; Tatsuji Matsuura; Masao Hotta (IEEE J. Solid State Circuits, 1995)

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits. - Keiko Makie-Fukuda; Takanobu Anbo; Toshiro Tsukada; Tatsuji Matsuura; Masao Hotta (IEEE J. Solid State Circuits, 1996)

Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor. - Keiko Makie-Fukuda; Takanobu Anbo; Toshiro Tsukada; Tatsuji Matsuura; Masao Hotta (IEEE J. Solid State Circuits, 1996)

Analog intellectual property: now? Or never? - Mike Brunoli; Masao Hotta; Felicia James; Rudy Koch; Roy McGuffin; Andrew J. Moore (DAC, 2002)

An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system. - Osamu Matsumoto; Hisashi Harada; Yasuo Morimoto; Toshio Kumamoto; Takahiro Miki; Masao Hotta (ASP-DAC, 2005)

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use. - Masao Hotta; Tatsuji Matsuura (IEICE Trans. Electron., 2006)

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. - Hao San; Akira Hayakawa; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Kazuyuki Kobayashi; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; et al. (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. - Masafumi Uemori; Haruo Kobayashi 001; Tomonari Ichikawa; Atsushi Wada; Koichiro Mashiko; Toshiro Tsukada; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Masao Hotta (ASP-DAC, 2007)

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; Toshiro Tsukada; et al. (IEICE Trans. Electron., 2007)

SAR ADC algorithm with redundancy. - Tomohiko Ogawa; Haruo Kobayashi 001; Masao Hotta; Yosuke Takahashi; Hao San; Nobukazu Takai (APCCAS, 2008)

A Time-to-Digital Converter with small circuitry. - Kazuya Shimizu; Masato Kaneta; HaiJun Lin; Haruo Kobayashi 001; Nobukazu Takai; Masao Hotta (ASP-DAC, 2009)

Non-binary SAR ADC with digital error correction for low power applications. - Tomohiko Ogawa; Tatsuji Matsuura; Haruo Kobayashi 001; Nobukazu Takai; Masao Hotta; Hao San; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (APCCAS, 2010)

SAR ADC Algorithm with Redundancy and Digital Error Correction. - Tomohiko Ogawa; Haruo Kobayashi 001; Yosuke Takahashi; Nobukazu Takai; Masao Hotta; Hao San; Tatsuji Matsuura; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique. - Koichi Ono; Takeshi Ohkawa; Masahiro Segami; Masao Hotta (IEICE Trans. Electron., 2010)

Rigorous analysis of quantization error of an A/D converter based on β-map. - Takaki Makino; Yukiko Iwata; Yutaka Jitsumatsu; Masao Hotta; Hao San; Kazuyuki Aihara (ISCAS, 2013)

Non-binary Pipeline Analog-to-Digital Converter Based on β-Expansion. - Hao San; Tomonari Kato; Tsubasa Maruyama; Kazuyuki Aihara; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Robust Cyclic ADC Architecture Based on β-Expansion. - Rie Suzuki; Tsubasa Maruyama; Hao San; Kazuyuki Aihara; Masao Hotta (IEICE Trans. Electron., 2013)

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. - Hao San; Rompei Sugawara; Masao Hotta; Tatsuji Matsuura; Kazuyuki Aihara (CICC, 2014)

Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm. - Rompei Sugawara; Hao San; Kazuyuki Aihara; Masao Hotta (IEICE Trans. Electron., 2014)

A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. - Yuta Mishima; Toshiki Yamada; Asato Uchiyama; Tatsuji Matsuura; Hao San; Masao Hotta (ISPACS, 2015)

Non-binary cyclic ADC with correlated level shifting technique. - Hiroyuki Tsuchiya; Asato Uchiyama; Yuta Misima; Yuki Watanabe; Tatsuji Matsuura; Hao San; Masao Hotta (ASP-DAC, 2017)

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. - Yuki Watanabe; Hayato Narita; Hiroyuki Tsuchiya; Tatsuji Matsuura; Hao San; Masao Hotta (ASP-DAC, 2017)

A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. - Koken Chin; Yuta Mishima; Yuki Watanabe; Hiroyuki Tsuchiya; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. - Hiroyuki Tsuchiya; Yuki Watanabe; Koken Chin; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

Experimental results of reconfigurable non-binary cyclic ADC. - Yuki Watanabe; Koken Chin; Hiroyuki Tsuchiya; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. - Hao San; Rompei Sugawara; Masao Hotta; Tatsuji Matsuura; Kazuyuki Aihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. - Shuichiro Yamada; Toshiki Ohtsu; Minami Sasaki; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2019)

A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. - Eiki Kayama; Kenta Mori; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. - Taichi Maebou; Yuanchi Chen; Eiki Kayama; Kenta Mori; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. - Kenta Mori; Eiki Kayama; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. - Eiki Kayama; Kenta Mori; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)