A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. - Bob Verbruggen; Masao Iriguchi; Jan Craninckx (ISSCC, 2012)

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. - Bob Verbruggen; Masao Iriguchi; Jan Craninckx (IEEE J. Solid State Circuits, 2012)

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. - Badr Malki; Bob Verbruggen; Piet Wambacq; Kazuaki Deguchi; Masao Iriguchi; Jan Craninckx (ESSCIRC, 2014)

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. - Bob Verbruggen; Jorgo Tsouhlarakis; Takaya Yamamoto; Masao Iriguchi; Ewout Martens; Jan Craninckx (IEEE J. Solid State Circuits, 2015)