A DSP line equalizer VLSI for TCM digital subscriber-line transmission. - Hideki Ando; Masao Nakaya; Hiroki Hona; Ihuo Iizuka; Yasutaka Horiba (IEEE J. Solid State Circuits, 1988)

An SOI structure for flash A/D converter. - Toshio Kumamoto; Masao Nakaya; Shigeru Kusunoki; Tadashi Nishimura; Nobuharu Yazawa; Yoichi Akasaka; Yasutaka Horiba (IEEE J. Solid State Circuits, 1988)

Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. - Hideki Ando; Chikako Nakanishi; Hirohisa Machida; Tetsuya Hara; Satoru Kishida; Masao Nakaya (ICCD, 1993)

A VLSI chip set for a large-scale parallel inference machine: PIM/m. - Hirohisa Machida; Hideki Ando; Kenichi Yasuda; Kiyohiro Furutani; Yukihiro Yamashita; Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Masayoshi Sakao; Masao Nakaya (IEEE J. Solid State Circuits, 1993)

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture. - Harufusa Kondoh; Hiromi Notani; Hideaki Yamanaka; Keiichi Higashitani; Hirotaka Saito; Isamu Hayashi; Shigeki Kohama; Yoshio Matsuda; Kazuyoshi Oshima; Masao Nakaya (IEEE J. Solid State Circuits, 1993)

Unconstrained Speculative Execution with Predicated State Buffering. - Hideki Ando; Chikako Nakanishi; Tetsuya Hara; Masao Nakaya (ISCA, 1995)

Code scheduling on a superscalar processor: SARCH. - Chikako Nakanishi; Hideki Ando; Hirohisa Machida; Masao Nakaya (Syst. Comput. Jpn., 1995)

Performance Comparison of ILP Machines with Cycle Time Evaluation. - Tetsuya Hara; Hideki Ando; Chikako Nakanishi; Masao Nakaya (ISCA, 1996)

Software pipelining with path selection. - Chikako Nakanishi; Hideki Ando; Tetsuya Hara; Masao Nakaya (Syst. Comput. Jpn., 1998)

SNDR sensitivity analysis for cascaded ΣΔ modulators. - James C. Morizio; Mike Hoke; Taskin Koçak; Clark Geddie; Chris Hughes; John Perry; Srinadh Madhavapeddi; Mike Hood; Ward Huffman; Takashi Okuda; Hiroshi Noda; Yasuo Morimoto; et al. (ISCAS, 2000)

14-bit 2.2-MS/s sigma-delta ADC's. - James C. Morizio; Michael Hoke; Taskin Koçak; Clark Geddie; Chris Hughes; John Perry; Srinadh Madhavapeddi; Michael H. Hood; George Lynch; Harufusa Kondoh; Toshio Kumamoto; Takashi Okuda; et al. (IEEE J. Solid State Circuits, 2000)

Roundtable: Envisioning the Future for Multiprocessor SoC. - Ahmed Amine Jerraya; Olivier Franza; Markus Levy; Masao Nakaya; Pierre G. Paulin; Ulrich Ramacher; Deepu Talla; Wayne H. Wolf (IEEE Des. Test Comput., 2007)

Special Section on Advanced Technologies in Digital LSIs and Memories. - Masao Nakaya (IEICE Trans. Electron., 2008)