On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. - Masao Naruse; Irith Pomeranz; Sudhakar M. Reddy; Sandip Kundu (ITC, 2003)

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. - Masao Naruse; Tatsuya Kamei; Toshihiro Hattori; Takahiro Irita; Kenichi Nitta; Takao Koike; Shinichi Yoshioka; Koji Ohno; Masahito Saigusa; Minoru Sakata; Yukio Kodama; Yuji Arai; et al. (ISSCC, 2008)

10.8 A multi-standard 2G/3G/4G Cellular modem supporting carrier aggregation in 28nm CMOS. - Michael Breschel; Peter Almers; Fredrik Angsmark; Alberth Arvidsson; Harald Bauer; Kees van Berkel 001; Joaquin Canovas; Minh Do; Anders Ekelund; Torsten Larsson; Bo Lincoln; Magnus Malmberg; et al. (ISSCC, 2014)