A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. - Nozomu Togawa; Takafumi Hisaki; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 1998)

An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. - Nozomu Togawa; Kayoko Hagi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 1998)

Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. - Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. - Nozomu Togawa; Takashi Sakurai; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 1999)

A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. - Nozomu Togawa; Kaoru Ukai; Masao Yanagisawa; Tatsuo Ohtsuki (J. Circuits Syst. Comput., 1999)

Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations. - Tingrong Zhao; Masao Yanagisawa; Tatsuo Ohtsuki (J. Circuits Syst. Comput., 1999)

An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). - Nozomu Togawa; Masayuki Ienaga; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2000)

Area/delay estimation for digital signal processor cores. - Yuichiro Miyaoka; Yoshiharu Kataoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2001)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. - Yuichiro Miyaoka; Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS (1), 2002)

VLSI Architecture for a Flexible Motion Estimation with Parameters. - Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC/VLSI Design, 2002)

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. - Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. - Shinichi Noda; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. - Shinichi Noda; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A hardware/software partitioning algorithm for SIMD processor cores. - Koichi Tachikake; Nozomu Togawa; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2003)

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. - Youhua Shi; Zhe Zhang; Shinji Kimura; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. - Nozomu Togawa; Kyosuke Kasahara; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. - Nozomu Togawa; Takao Totsuka; Tatsuhiko Wakui; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A cosynthesis algorithm for application specific processors with heterogeneous datapaths. - Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

Instruction set and functional unit synthesis for SIMD processor cores. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

A thread partitioning algorithm in low power high-level synthesis. - Jumpei Uchida; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. - Youhua Shi; Shinji Kimura; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (Asian Test Symposium, 2004)

A processor core synthesis system in IP-based SoC design. - Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2005)

Low Power Test Compression Technique for Designs with Multiple Scan Chain. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki; Shinji Kimura (Asian Test Symposium, 2005)

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. - Nozomu Togawa; Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS (4), 2005)

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. - Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Inf. Syst., 2005)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. - Shunitsu Kohara; Naoki Tomono; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. - Youhua Shi; Nozomu Togawa; Shinji Kimura; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. - Gang Zeng; Youhua Shi; Toshinori Takabatake; Masao Yanagisawa; Hideo Ito (DFT, 2006)

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. - Youhua Shi; Nozomu Togawa; Shinji Kimura; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. - Jumpei Uchida; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Electron., 2006)

Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS, 2007)

Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: evaluation by large-scale real data. - Shuichi Takitoh; Shogo Fujii; Yoichi Mase; Junichi Takasaki; Toshimasa Yamazaki; Yozo Ohnishi; Masao Yanagisawa; Yusuke Nakamura; Naoyuki Kamatani (Bioinform., 2007)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. - Akiyuki Nagashima; Yuta Imai; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS, 2008)

Unknown response masking with minimized observable response loss and mask data. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS, 2008)

FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. - Ryo Tamura; Masayuki Honma; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki; Makoto Satoh (APCCAS, 2008)

GECOM: Test data compression combined with all unknown response masking. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2008)

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Kazunori Shimizu; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2008)

A Secure Test Technique for Pipelined Advanced Encryption Standard. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Inf. Syst., 2008)

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. - Akira Ohchi; Shunitsu Kohara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Robust estimation of the arterial input function for Logan plots using an intersectional searching algorithm and clustering in positron emission tomography for neuroreceptor imaging. - Mika Naganawa; Yuichi Kimura; Junichi Yano; Masahiro Mishina; Masao Yanagisawa; Kenji Ishii; Keiichi Oda; Kiichi Ishiwata (NeuroImage, 2008)

Exact and fast L1 cache simulation for embedded systems. - Nobuaki Tojo; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2009)

Design-for-secure-test for crypto cores. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ITC, 2009)

A Scan-Based Attack Based on Discriminators for AES Cryptosystems. - Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. - Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An L1 Cache Design Space Exploration System for Embedded Applications. - Nobuaki Tojo; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Two-Level Cache Design Space Exploration System for Embedded Applications. - Nobuaki Tojo; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. - Seungju Lee; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (APCCAS, 2010)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. - Youhua Shi; Kenta Tokumitsu; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS, 2010)

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. - Youhei Tsukamoto; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (APCCAS, 2010)

Scan-based attack against elliptic curve cryptosystems. - Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2010)

State-dependent changeable scan architecture against scan-based side channel attacks. - Ryuta Nara; Hiroshi Atobe; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS, 2010)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. - Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS, 2010)

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. - Ryuta Nara; Kei Satoh; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Improved Launch for Higher TDF Coverage With Fewer Test Patterns. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Speeding-up exact and fast FIFO-based cache configuration simulation. - Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2011)

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. - Mikiko Sode Tanaka; Nozomu Togawa; Masao Yanagisawa; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. - Mikiko Sode Tanaka; Nozomu Togawa; Masao Yanagisawa; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Scan Vulnerability in Elliptic Curve Cryptosystems. - Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. - Sho Tanaka; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. - Masashi Tawada; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. - Youhei Tsukamoto; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. - Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2012)

Scan-based attack against DES cryptosystems using scan signatures. - Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2012)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. - Hiromine Yoshihara; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2012)

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. - Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2012)

Energy-efficient high-level synthesis for HDR architectures with clock gating. - Hiroyuki Akasaka; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2012)

Dynamically changeable secure scan architecture against scan-based side channel attack. - Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2012)

MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. - Shin-ya Abe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2012)

A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. - Seungju Lee; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Scan-Based Attack on AES through Round Registers and Its Countermeasure. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Energy-efficient High-level Synthesis for HDR Architectures. - Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. - Hiromine Yoshihara; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

Integrating Wearable Sensor Technology into Project-management Process. - Koji Ara; Tomoaki Akitomi; Nobuo Sato; Kunio Takahashi; Hideyuki Maeda; Kazuo Yano; Masao Yanagisawa (J. Inf. Process., 2012)

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Scan-based attack against Trivium stream cipher independent of scan structure. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (ASICON, 2013)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. - Shota Matsuno; Masashi Tawada; Masao Yanagisawa; Shinji Kimura; Nozomu Togawa; Tadahiko Sugibayashi (ASICON, 2013)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. - Hiroaki Igarashi; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2013)

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. - Kazushi Kawamura; Sho Tanaka; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2013)

Suspicious timing error prediction with in-cycle clock gating. - Youhua Shi; Hiroaki Igarashi; Nozomu Togawa; Masao Yanagisawa (ISQED, 2013)

Secure Scan Design with Dynamically Configurable Connection. - Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (PRDC, 2013)

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. - Shin-ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa (VLSI-DAT, 2013)

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. - Shin-ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. - Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. - Hiroyuki Akasaka; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. - Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (J. Inf. Process., 2013)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. - Koichi Fujiwara; Shin-ya Abe; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

Scan-based side-channel attack on Camellia cipher using scan signatures. - Huiqian Hang; Mika Fujishiro; Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

A write-reducing and error-correcting code generation method for non-volatile memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

Secure scan design using improved random order and its evaluations. - Masaru Oya; Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. - Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

Scan-based attack on the LED block cipher using scan signatures. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2014)

Linear and bi-linear interpolation circuits using selector logics and their evaluations. - Masashi Shio; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2014)

Throughput driven check point selection in suspicious timing error prediction based designs. - Hiroaki Igarashi; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (LASCAS, 2014)

Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. - Hiroyuki Akasaka; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. - Yuta Hagio; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Clock skew estimate modeling for FPGA high-level synthesis and its application. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. - Keita Igarashi; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

Small-sized and noise-reducing power analyzer design for low-power IoT devices. - Ryosuke Kitayama; Takashi Takenaka; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

A low-power soft error tolerant latch scheme. - Saki Tajima; Youhua Shi; Nozomu Togawa; Masao Yanagisawa (ASICON, 2015)

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. - Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

A bit-write reduction method based on error-correcting codes for non-volatile memories. - Masashi Tawada; Shinji Kimura; Masao Yanagisawa; Nozomu Togawa (ASP-DAC, 2015)

A score-based classification method for identifying hardware-trojans at gate-level netlists. - Masaru Oya; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (DATE, 2015)

A landmark-based route recommendation method for pedestrian walking strategies. - Siya Bao; Tomoyuki Nitta; Daisuke Shindou; Masao Yanagisawa; Nozomu Togawa (GCCE, 2015)

A visible corner-landmark based route finding algorithm for pedestrian navigation. - Kengo Takeda; Tomoyuki Nitta; Daisuke Shindou; Masao Yanagisawa; Nozomu Togawa (GCCE, 2015)

Muscle analysis of hand and forearm during tapping using surface electromyography. - Masayuki Yokoyama; Ryohei Koyama; Masao Yanagisawa (GCCE, 2015)

Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (ICCAD, 2015)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2015)

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. - Koki Igawa; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (SoCC, 2015)

Partitioning-based multiplexer network synthesis for field-data extractors. - Koki Ito; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (SoCC, 2015)

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. - Shin-ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. - Koichi Fujiwara; Kazushi Kawamura; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. - Huiqian Jiang; Mika Fujishiro; Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. - Masaru Oya; Youhua Shi; Noritaka Yamashita; Toshihiko Okamura; Yukiyasu Tsunoo; Satoshi Goto; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. - Masashi Tawada; Shinji Kimura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. - Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Implementation evaluation of scan-based attack against a Trivium cipher circuit. - Daisuke Oku; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2016)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark. - Siya Bao; Tomoyuki Nitta; Kazuaki Ishikawa; Masao Yanagisawa; Nozomu Togawa (GCCE, 2016)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. - Keisuke Kono; Tomoyuki Nitta; Kazuaki Ishikawa; Masao Yanagisawa; Nozomu Togawa (GCCE, 2016)

Pedestrian navigation based on landmark recognition using glass-type wearable devices. - Ryoya Yano; Tomoyuki Nitta; Kazuaki Ishikawa; Masao Yanagisawa; Nozomu Togawa (GCCE, 2016)

Hardware Trojans classification for gate-level netlists based on machine learning. - Kento Hasegawa; Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2016)

Redesign for untrusted gate-level netlists. - Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2016)

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. - Ryosuke Kitayama; Takashi Takenaka; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2016)

A high-performance circuit design algorithm using data dependent approximation. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2016)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing. - Koki Igawa; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISQED, 2016)

In-situ Trojan authentication for invalidating hardware-Trojan functions. - Masaru Oya; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISQED, 2016)

Rotator-based multiplexer network synthesis for field-data extractors. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (SoCC, 2016)

Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2016)

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. - Ryosuke Kitayama; Takashi Takenaka; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. - Masaru Oya; Noritaka Yamashita; Toshihiko Okamura; Yukiyasu Tsunoo; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. - Daiki Asai; Masao Yanagisawa; Nozomu Togawa (ASICON, 2017)

Designing hardware trojans and their detection based on a SVM-based approach. - Tomotaka Inoue; Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ASICON, 2017)

Soft error tolerant latch designs with low power consumption (invited paper). - Saki Tajima; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (ASICON, 2017)

A low cost and high speed CSD-based symmetric transpose block FIR implementation. - Jinghao Ye; Youhua Shi; Nozomu Togawa; Masao Yanagisawa (ASICON, 2017)

A stayed location estimation method for sparse GPS positioning information. - Sae Iwata; Tomoyuki Nitta; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (GCCE, 2017)

An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. - Ryoya Momose; Tomoyuki Nitta; Masao Yanagisawa; Nozomu Togawa (GCCE, 2017)

Personalized one-day travel with multi-nearby-landmark recommendation. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2017)

A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. - Daisuke Oku; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2017)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2017)

Hardware Trojan detection and classification based on steady state learning. - Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2017)

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2017)

Effective write-reduction method for MLC non-volatile memory. - Masashi Tawada; Shinji Kimura; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2017)

A selector-based FFT processor and its FPGA implementation. - Yuya Hirai; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2017)

Robust AES circuit design for delay variation using suspicious timing error prediction. - Yuki Yahagi; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2017)

A proposal for wearable controller device and finger gesture recognition using surface electromyography. - Ayumu Tsuboi; Mamoru Hirota; Junki Sato; Masayuki Yokoyama; Masao Yanagisawa (SIGGRAPH ASIA (Posters), 2017)

A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. - Siya Bao; Tomoyuki Nitta; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices. - Masayuki Yokoyama; Ryohei Koyama; Masao Yanagisawa (J. Sensors, 2017)

Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (IEEE BigData, 2018)

Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. - Tomotaka Inoue; Kento Hasegawa; Yuki Kobayashi; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. - Sae Iwata; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. - Tensei Nishimura; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

Bicycle Behavior Recognition using Sensors Equipped with Smartphone. - Yuri Usami; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

Road-illuminance level inference across road networks based on Bayesian analysis. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (ICCE, 2018)

A hardware-Trojan classification method utilizing boundary net structures. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ICCE, 2018)

Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2018)

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2018)

A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2018)

A loop structure optimization targeting high-level synthesis of fast number theoretic transform. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISQED, 2018)

2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (NGCAS, 2018)

Gesture recognition of air-tapping and its application to character input in VR space. - Mamoru Hirota; Ayumu Tsuboi; Masayuki Yokoyama; Masao Yanagisawa (SIGGRAPH ASIA Posters, 2018)

An Ising model mapping to solve rectangle packing problem. - Kotaro Terada; Daisuke Oku; Sho Kanamaru; Shu Tanaka; Masato Hayashi; Masanao Yamaoka; Masao Yanagisawa; Nozomu Togawa (VLSI-DAT, 2018)

Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. - Ken Hayamizu; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. - Sae Iwata; Tomoyuki Nitta; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. - Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. - Saki Tajima; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. - Daisuke Oku; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2018)

A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (ICIS (best papers), 2019)

A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (APCCAS, 2019)

A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. - Lin Ye; Jinghao Ye; Masao Yanagisawa; Youhua Shi (APCCAS, 2019)

An Adder-Segmentation-based FIR for High Speed Signal Processing. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (ASICON, 2019)

Efficient Ising Model Mapping to Solving Slot Placement Problem. - Sho Kanamaru; Daisuke Oku; Masashi Tawada; Shu Tanaka; Masato Hayashi; Masanao Yamaoka; Masao Yanagisawa; Nozomu Togawa (ICCE, 2019)

Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (ICECS, 2019)

Error Correction Coding of Stochastic Numbers Using BER Measurement. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2019)

Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. - Jinghao Ye; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (ISCAS, 2019)

A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. - Sae Iwata; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. - Tensei Nishimura; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. - Yuri Usami; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

An FPGA Implementation Method based on Distributed-register Architectures. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (APCCAS, 2020)

Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (LASCAS, 2020)

Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Inf. Syst., 2020)

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. - Saki Tajima; Masao Yanagisawa; Youhua Shi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. - Lin Ye; Jinghao Ye; Masao Yanagisawa; Youhua Shi (IEEE Access, 2021)

An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. - Jiaxiang Li; Masao Yanagisawa; Youhua Shi (ASICON, 2023)

Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. - Yirui Su; Masao Yanagisawa; Youhua Shi (ICICDT, 2023)

An FPGA-Based YOLOv6 Accelerator for High-Throughput and Energy-Efficient Object Detection. - Xingan Sha; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

DSE-Based Hardware Trojan Attack for Neural Network Accelerators on FPGAs. - Chao Guo; Masao Yanagisawa; Youhua Shi (IEEE Trans. Neural Networks Learn. Syst., 2025)