A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. - Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; et al. (IEEE J. Solid State Circuits, 2000)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs. - Takeshi Fujino; Akira Yamazaki; Yasuhiko Taito; Mitsuya Kinoshita; Fukashi Morishita; Teruhiko Amano; Masaru Haraguchi; Makoto Hatakenaka; Atsushi Amo; Atsushi Hachisuka; Kazutami Arimoto; Hideyuki Ozaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. - Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (ISSCC, 2007)

A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (IEICE Trans. Electron., 2009)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)