Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. - Masaru Kato; Yohei Hasegawa; Hideharu Amano (ERSA, 2008)

Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. - Toru Sano; Masaru Kato; Satoshi Tsutsumi; Yohei Hasegawa; Hideharu Amano (FPL, 2008)

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. - Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (ERSA, 2009)

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. - Toru Sano; Yoshiki Saito; Masaru Kato; Hideharu Amano (FPL, 2009)

Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. - Keiichiro Hirai; Masaru Kato; Yoshiki Saito; Hideharu Amano (FPT, 2009)

MuCCRA-3: a low power dynamically reconfigurable processor array. - Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Masayuki Kimura; Hideharu Amano (ASP-DAC, 2010)

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. - Kazuei Hironaka; Masayuki Kimura; Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (FPT, 2010)

Correcting for non-uniform illumination when photographing the mural in the royal tomb of Amenophis III (III) Correcting mural images. - Masao Inui; Masaru Kato; Keitaro Inomata; Machiko Sato; Yoshihiko Azuma; Daisuke Saito; Tota Mizuno; Takao Kikuchi; Sakuji Yoshimura (CGIV, 2012)