Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. - Kimiyoshi Usami; Masaru Kudo; Kensaku Matsunaga; Tsubasa Kosaka; Yoshihiro Tsurui; Weihan Wang; Hideharu Amano; Hiroaki Kobayashi; Ryuichi Sakamoto; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ASP-DAC, 2014)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. - Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; et al. (COOL Chips, 2014)

Design and evaluation of fine-grained power-gating for embedded microprocessors. - Masaaki Kondo; Hiroaki Kobayashi; Ryuichi Sakamoto; Motoki Wada; Jun Tsukamoto; Mitaro Namiki; Weihan Wang; Hideharu Amano; Kensaku Matsunaga; Masaru Kudo; Kimiyoshi Usami; Toshiya Komoda; et al. (DATE, 2014)

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. - Kimiyoshi Usami; Makoto Miyauchi; Masaru Kudo; Kazumitsu Takagi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ISSoC, 2014)

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor. - Masaru Kudo; Kimiyoshi Usami (NVMSA, 2017)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. - Kimiyoshi Usami; Junya Akaike; Sosuke Akiba; Masaru Kudo; Hideharu Amano; Takeharu Ikezoe; Keizo Hiraga; Yusuke Shuto; Kojiro Yagami (NVMSA, 2018)

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. - Takeharu Ikezoe; Hideharu Amano; Junya Akaike; Kimiyoshi Usami; Masaru Kudo; Keizo Hiraga; Yusuke Shuto; Kojiro Yagami (ReConFig, 2018)