A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. - Masaru Osada; Zule Xu; Tetsuya Iizuka (VLSI Circuits, 2020)

A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. - Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Circuits, 2021)

An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. - Masaru Osada; Zule Xu; Tetsuya Iizuka (ESSCIRC, 2022)

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. - Zunsong Yang; Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Technology and Circuits, 2022)

Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. - Masaru Osada; Zule Xu; Ryoya Shibata; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. - Zunsong Yang; Masaru Osada; Shuowei Li; Yuyang Zhu; Tetsuya Iizuka (VLSI Technology and Circuits, 2023)

Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. - Yuyang Zhu; Zunsong Yang; Masaru Osada; Haoming Zhang; Tetsuya Iizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. - Masaru Osada; Zule Xu; Zunsong Yang; Tetsuya Iizuka (IEEE J. Solid State Circuits, 2024)

A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellation. - Haoming Zhang; Yuyang Zhu; Masaru Osada; Tetsuya Iizuka (ISSCC, 2025)

A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation. - Haoming Zhang; Masaru Osada; Yuyang Zhu; Tetsuya Iizuka (IEEE J. Solid State Circuits, 2025)

Optimization of DTC-Based and Harmonic-Mixer-Based Fractional-N PLLs: Comparative Analysis of Jitter and Power Trade-Offs. - Yuyang Zhu; Masaru Osada; Haoming Zhang; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)