Study on maximum electric field modeling used for HCI induced degradation characteristic of LDMOS transistors. - Masashi Higashino; Hitoshi Aoki; Nobukazu Tsukiji; Masaki Kazumi; Takuya Totsuka; Haruo Kobayashi 001 (ASICON, 2015)

A study on HCI induced gate leakage current model used for reliability simulations in 90nm n-MOSFETs. - Nobukazu Tsukiji; Hitoshi Aoki; Masaki Kazumi; Takuya Totsuka; Masashi Higashino; Haruo Kobayashi 001 (ASICON, 2015)

DAC linearity improvement with layout technique using magic and latin squares. - Dan Yao; Yifei Sun 001; Masashi Higashino; Shaiful Nizam Bin Mohyar; Tomonori Yanagida; Takuya Arafune; Nobukazu Tsukiji; Haruo Kobayashi 001 (ISPACS, 2017)