An experimental large-capacity semiconductor file memory using 16-levels/cell storage. - Masashi Horiguchi; Masakazu Aoki; Yoshinobu Nakagome; Shin'ichi Ikenaga; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1988)

New DRAM noise generation under half-Vcc precharge and its reduction using a transposed amplifier. - Masakazu Aoki; Shin'ichi Ikenaga; Yoshinobu Nakagome; Masashi Horiguchi; Yasushi Kawase; Yoshifumi Kawamoto; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1989)

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Hitoshi Tanaka; Shin'ichi Ikenaga; Kiyoo Itoh 001; Kazuhiko Kajigaya; Hiroaki Kotani; Kazuyoshi Ohshima; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1990)

A flexible redundancy technique for high-density DRAMs. - Masashi Horiguchi; Jun Etoh; Masakazu Aoki; Kiyoo Itoh 001; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test. - Masashi Horiguchi; Masakazu Aoki; Jun Etoh; Gyoo Itoh; Kazuhiko Kajigaya; Atsushi Nozoe; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1991)

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's. - Masashi Horiguchi; Takeshi Sakata; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1993)

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). - Takayuki Kawahara; Masashi Horiguchi; Yoshiki Kawajiri; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

256-Mb DRAM circuit technologies for file applications. - Goro Kitsukawa; Masashi Horiguchi; Yoshiki Kawajiri; Takayuki Kawahara; Takesada Akiba; Yasushi Kawase; Toshikazu Tachibana; Takeshi Sakai; Masakazu Aoki; Syoji Shukuri; Kazuhiko Sagara; Ryo Nagai; et al. (IEEE J. Solid State Circuits, 1993)

A charge recycle refresh for Gb-scale DRAM's in file applications. - Takayulu Kawahara; Yoshiki Kawajiri; Masashi Horiguchi; Takesada Akiba; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

Subthreshold-current reduction circuits for multi-gigabit DRAM's. - Takeshi Sakata; Kiyoo Itoh 001; Masashi Horiguchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. - Takeshi Sakata; Kiyoo Itoh 001; Masashi Horiguchi; Masakazu Aoki (IEEE J. Solid State Circuits, 1994)

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)

Low-noise, high-speed data transmission using a ringing-canceling output buffer. - Tomonori Sekiguchi; Masashi Horiguchi; Takeshi Sakata; Yoshinobu Nakagome; Shigeki Ueda; Masakazu Aoki (IEEE J. Solid State Circuits, 1995)

Review and future prospects of low-voltage RAM circuits. - Yoshinobu Nakagome; Masashi Horiguchi; Takayuki Kawahara; Kiyoo Itoh 001 (IBM J. Res. Dev., 2003)

Ultra-low voltage nano-scale embedded RAMs. - Kiyoo Itoh 001; Masashi Horiguchi; Takayuki Kawahara (ISCAS, 2006)

Low-voltage limitations of memory-rich nano-scale CMOS LSIs. - Kiyoo Itoh 001; Masashi Horiguchi; Masanao Yamaoka (ESSCIRC, 2007)

Ultra-Low Voltage Nano-Scale Memories - Kiyoo Itoh 001; Masashi Horiguchi; Hitoshi Tanaka (Springer, 2007)

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. - Akira Kotabe; Kiyoo Itoh 001; Riichiro Takemura; Ryuta Tsuchiya; Masashi Horiguchi (CICC, 2011)

Nanoscale Memory Repair - Masashi Horiguchi; Kiyoo Itoh 001 (Springer, 2011)

A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensation. - Shinya Sano; Yasuhiko Takahashi; Masashi Horiguchi; Moriyoshi Ota (VLSIC, 2012)

Simple Reference Voltage Generation Circuit Insensitive to Temperature. - Lei Sha; Anna Kuwana; Masashi Horiguchi; Haruo Kobayashi 001 (ISOCC, 2020)