TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. - Akihiro Takamura; Masashi Kuwako; Masashi Imai; Taro Fujii; Motokazu Ozawa; Izumi Fukasaku; Yoichiro Ueno; Takashi Nanya (ICCD, 1997)

TITAC-2: An Asynchronous 32-bit Microprocessor. - Akihiro Takamura; Motokazu Ozawa; Izumi Fukasaku; Taro Fujii; Yoichiro Ueno; Masashi Imai; Masashi Kuwako; Takashi Nanya (ASP-DAC, 1998)

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. - Motokazu Ozawa; Masashi Imai; Hiroshi Nakamura; Takashi Nanya; Yoichiro Ueno (ASYNC, 2001)

Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. - T. Ohneda; Masaaki Kondo; Masashi Imai; Hiroshi Nakamura (APCCAS (1), 2002)

Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. - Metehan Özcan; Masashi Imai; Takashi Nanya (ASYNC, 2002)

High Throughput Asynchronous Domino Using Dual output Buffer. - Masayuki Tsukisaka; Masashi Imai; Takashi Nanya (IWLS, 2002)

Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. - Hiroshi Saito; Euiseok Kim; Nattha Sretasereekul; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (ASYNC, 2003)

Control signal sharing of asynchronous circuits using datapath delay information. - Hiroshi Saito; Euiseok Kim; Masashi Imai; Nattha Sretasereekul; Hiroshi Nakamura; Takashi Nanya (ISCAS (5), 2003)

A zero-time-overhead asynchronous four-phase controller. - Nattha Sretasereekul; Hiroshi Saito; Masashi Imai; Euiseok Kim; Metehan Özcan; K. Thongnoo; Hiroshi Nakamura; Takashi Nanya (ISCAS (5), 2003)

Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. - Nattha Sretasereekul; Hiroshi Saito; Euiseok Kim; Metehan Özcan; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. - Masashi Imai; Metehan Özcan; Takashi Nanya (ASYNC, 2004)

Asynchronous Scan-Latch controller for Low Area Overhead DFT. - Masayuki Tsukisaka; Masashi Imai; Takashi Nanya (ICCD, 2004)

Skewed Checkpointing for Tolerating Multi-Node Failures. - Hiroshi Nakamura; Takuro Hayashida; Masaaki Kondo; Yuya Tajima; Masashi Imai; Takashi Nanya (SRDS, 2004)

A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. - Masashi Imai; Takashi Nanya (ASYNC, 2006)

Design Method of High Performance and Low Power Functional Units Considering Delay Variations. - Kouichi Watanabe; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. - Ryo Watanabe; Masaaki Kondo; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (DATE, 2007)

A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. - Masashi Imai; Takashi Nanya (ACSD, 2008)

Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. - Masashi Imai; Kouei Takada; Takashi Nanya (ASYNC, 2009)

N-way ring and square arbiters. - Masashi Imai; Tomohiro Yoneda; Takashi Nanya (ICCD, 2009)

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. - Kimiyoshi Usami; Toshiaki Shirai; Tatsunori Hashida; Hiroki Masuda; Seidai Takeda; Mitsutaka Nakata; Naomi Seki; Hideharu Amano; Mitaro Namiki; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura (VLSI Design, 2009)

Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. - Masashi Imai; Tomohide Nagai; Takashi Nanya (DSN Workshops, 2010)

An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. - James L. Weston; Masashi Imai; Tomohide Nagai; Takashi Nanya (PRDC, 2010)

Improving Dependability and Performance of Fully Asynchronous On-chip Networks. - Masashi Imai; Tomohiro Yoneda (ASYNC, 2011)

Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. - Masashi Imai; Tomohiro Yoneda (DFT, 2011)

Dependable routing in multi-chip NoC platforms for automotive applications. - Tomohiro Yoneda; Masashi Imai (DFT, 2012)

Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. - Masashi Imai; Tomohiro Yoneda (PRDC, 2012)

Multi-chip NoCs for Automotive Applications. - Tomohiro Yoneda; Masashi Imai; Naoya Onizawa; Atsushi Matsumoto; Takahiro Hanyu (PRDC, 2012)

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. - Masashi Imai; Tomohiro Yoneda (IEICE Trans. Inf. Syst., 2013)

Modeling of substrate contacts in TSV-based 3D ICs. - Masayuki Watanabe; Masa-Aki Fukase; Masashi Imai; Nanako Niioka; Tetsuya Kobayashi; Rosely Karel; Atsushi Kurokawa (3DIC, 2014)

Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. - Masashi Imai; Tomohiro Yoneda (APCCAS, 2014)

Impact of on-chip interconnects on vertical signal propagation in 3D ICs. - Nanako Niioka; Masayuki Watanabe; Rosely Karel; Tetsuya Kobayashi; Masashi Imai; Masa-Aki Fukase; Atsushi Kurokawa (APCCAS, 2014)

Effect of substrate contacts on reducing crosstalk noise between TSVs. - Masayuki Watanabe; Rosely Karel; Nanako Niioka; Tetsuya Kobayashi; Masa-Aki Fukase; Masashi Imai; Atsushi Kurokawa (APCCAS, 2014)

An NoC-based evaluation platform for safety-critical automotive applications. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Takahiro Hanyu; Kenji Kise; Yuichi Nakamura 002 (APCCAS, 2014)

Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. - Masashi Imai; Tomohiro Yoneda (ISCAS, 2014)

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. - Naoya Onizawa; Akira Mochizuki; Hirokatsu Shirahama; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (IEICE Trans. Inf. Syst., 2014)

Dependable real-time task execution scheme for a many-core platform. - Tomohiro Yoneda; Masashi Imai; Hiroshi Saito; Kenji Kise (DFTS, 2015)

A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. - Tomohiro Yoneda; Masashi Imai (ICCD, 2015)

Clock skew reduction for stacked chips using multiple source buffers. - Nanako Niioka; Masashi Imai; Masa-Aki Fukase; Yuuki Miura; Kaoru Furumi; Atsushi Kurokawa (ISCIT, 2015)

An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. - Masayuki Watanabe; Nanako Niioka; Tetsuya Kobayashi; Rosely Karel; Masa-Aki Fukase; Masashi Imai; Atsushi Kurokawa (ISQED, 2015)

Novel Implementation Method of Multiple-Way Asynchronous Arbiters. - Masashi Imai; Tomohiro Yoneda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Signal Propagation Delay Model in Vertically Stacked Chips. - Nanako Niioka; Masayuki Watanabe; Masa-Aki Fukase; Masashi Imai; Atsushi Kurokawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A task allocation method for the DTTR scheme based on task scheduling of fault patterns. - Hiroshi Saito; Masashi Imai; Tomohiro Yoneda (ISCAS, 2016)

A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. - Hiroshi Saito; Masashi Imai; Tomohiro Yoneda (MCSoC, 2016)

The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. - Masashi Imai; Thiem Van Chu; Kenji Kise; Tomohiro Yoneda (NOCS, 2016)

Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. - Kaoru Furumi; Masashi Imai; Atsushi Kurokawa (ISQED, 2017)

Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. - Hiroshi Saito; Masashi Imai; Tomohiro Yoneda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. - Masashi Imai; Shinichiro Akasaka; Tomohiro Yoneda (ASYNC, 2018)

MTJ-based asynchronous circuits for Re-initialization free computing against power failures. - Naoya Onizawa; Masashi Imai; Tomohiro Yoneda; Takahiro Hanyu (Microelectron. J., 2018)

Hardware Trojan Insertion and Detection in Asynchronous Circuits. - Koutaro Inaba; Tomohiro Yoneda; Toshiki Kanamoto; Atsushi Kurokawa; Masashi Imai (ASYNC, 2019)

A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. - Toshiki Kanamoto; Masami Fukushima; Koichi Kitagishi; Seijin Nakayama; Hideki Ishihara; Koki Kasai; Atsushi Kurokawa; Masashi Imai (MWSCAS, 2019)

Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). - Tomohiro Yoneda; Peter A. Beerel; Alex Yakovlev; Masashi Imai (NII Shonan Meet. Rep., 2019)

Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. - Tomohiro Yoneda; Masashi Imai (ASYNC, 2020)

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. - Toshiki Kanamoto; Koki Kasai; Kan Hatakeyama; Atsushi Kurokawa; Tomoyuki Nagase; Masashi Imai (IEICE Electron. Express, 2020)

An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring. - Kan Hatakeyama; Seria Kasai; Masashi Imai; Atsushi Kurokawa; Masami Fukushima; Koichi Kitagishi; Seijin Nakayama; Hideki Ishihara (GCCE, 2021)

Simulation and Evaluation of Asynchronous Circuits in Extreme Edge Environments. - Masashi Imai (ISMVL, 2025)