Timing-reliability evaluation of asynchronous circuits based on different delay models. - Masashi Kuwako; Takashi Nanya (ASYNC, 1994)

TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. - Takashi Nanya; Yoichiro Ueno; Hiroto Kagotani; Masashi Kuwako; Akihiro Takamura (IEEE Des. Test Comput., 1994)

TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. - Akihiro Takamura; Masashi Kuwako; Masashi Imai; Taro Fujii; Motokazu Ozawa; Izumi Fukasaku; Yoichiro Ueno; Takashi Nanya (ICCD, 1997)

TITAC-2: An Asynchronous 32-bit Microprocessor. - Akihiro Takamura; Motokazu Ozawa; Izumi Fukasaku; Taro Fujii; Yoichiro Ueno; Masashi Imai; Masashi Kuwako; Takashi Nanya (ASP-DAC, 1998)