A 5.3-GB/s embedded SDRAM core with slight-boost scheme. - Akira Yamazaki; Tadato Yamagata; Makoto Hatakenaka; Atsushi Miyanishi; Isao Hayashi; Shigeki Tomishima; Atsuo Mangyo; Yoshio Yukinari; Takashi Tatsumi; Masashi Matsumura; Kazutami Arimoto; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)