An approach to consistent jitter modeling for various jitter aspects and measurement methods. - Masashi Shimanouchi (ITC, 2001)

New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing. - Masashi Shimanouchi (ITC, 2002)

Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production. - Masashi Shimanouchi (ITC, 2003)

Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE. - Masashi Shimanouchi (ITC, 2004)

Tester Architecture For The Source Synchronous Bus. - A. T. Sivaram; Masashi Shimanouchi; Howard Maassen; Robert Jackson (ITC, 2004)

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing. - Masashi Shimanouchi; Mike Peng Li; Daniel Chow (ITC, 2009)

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013). - Mike Peng Li; Masashi Shimanouchi; Hsinho Wu (CICC, 2013)

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities. - Daniel Chow; Masashi Shimanouchi; Mike Peng Li (ITC, 2013)

SERDES external loopback test using production parametric-test hardware. - Shalini Arora; Aman Aflaki; Sounil Biswas; Masashi Shimanouchi (ITC, 2016)

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. - Jihwan Kim; Ariel Cohen 001; Mike Peng Li; Ajay Balankutty; Sandipan Kundu; Ahmad Khairi; Yoel Krupnik; Yoav Segal; Marco Cusmai; Dror Lazar; Ari Gordon; Noam Familia; et al. (CICC, 2024)