An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. - Masataka Matsui; Hiroshi Momose; Yukihiro Urakawa; Takeo Maeda; Azuma Suzuki; Nobuaki Urakawa; Katsuhiko Sato; Jun'ichi Matsunaga; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1989)

Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs. - Hideo Kato; Katsuhiko Sato; Masataka Matsui; H. Shibata; K. Hashimoto; Takayuki Ootani; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1992)

A 110-MHz/1-Mb synchronous TagRAM. - Yasuo Unekawa; Tsuguo Kobayashi; Tsukasa Shirotori; Yukihiro Fujimoto; Takayoshi Shimazawa; Kazutaka Nogami; Takehiko Nakao; Kazukiro Sawada; Masataka Matsui; Takayasu Sakurai; Man Kit Tang; William A. Huffman (IEEE J. Solid State Circuits, 1994)

A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. - Masataka Matsui; Hiroyuki Hara; Yoshiharu Uetani; Lee-Sup Kim; Tetsu Nagamatsu; Yoshinori Watanabe; Akihiko Chiba; Kouji Matsuda; Takayasu Sakurai (IEEE J. Solid State Circuits, 1994)

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober. - Hideo Kato; Masataka Matsui; Katsuhiko Sato; H. Shibata; K. Hashimoto; Takayuki Ootani; Kiyofumi Ochii (IEEE J. Solid State Circuits, 1997)

Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. - Norman Kojima; Yukiko Parameswar; Christian Klingner; Yukio Ohtaguro; Masataka Matsui; Shigeaki Iwasa; Tatsuo Teruyama; Takayoshi Shimazawa; Hideki Takeda; Kouji Hashizume; Haruyuki Tago; Masaaki Yamada (ASP-DAC, 2000)

Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. - Vjekoslav Svilan; Masataka Matsui; James B. Burr (ISLPED, 2000)

A single-chip MPEG-2 codec based on customizable media microprocessor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (CICC, 2002)

Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. - Atsushi Mizuno; Kazuyoshi Kohno; Ryuichiro Ohyama; Takahiro Tokuyoshi; Hironori Uetani; Hans Eichel; Takashi Miyamori; Nobu Matsumoto; Masataka Matsui (ICCD, 2002)

Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. - Jun Tanahe; Yasuhiro Taniguchi; Takashi Miyamori; Yukimasa Miyamoto; Hideki Takeda; Masaya Tarui; Hiromitsu Nakayama; Nohuyulu Takeda; Kenichi Maeda; Masataka Matsui (CICC, 2003)

A single-chip MPEG-2 codec based on customizable media embedded processor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (IEEE J. Solid State Circuits, 2003)

DSP for wireless. - Lawrence Clark; Masataka Matsui (CICC, 2005)

Development of Image Recognition Processor Based on Configurable Processor. - Takashi Miyamori; Jun Tanabe; Yasuhiro Taniguchi; Kenji Furukawa; Tatsuo Kozakaya; Hiroaki Nakai; Yukimasa Miyamoto; Ken-ichi Maeda; Masataka Matsui (J. Robotics Mechatronics, 2005)

Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding. - Shen Li; Lingfeng Li; Takeshi Ikenaga; Shunichi Ishiwata; Masataka Matsui; Satoshi Goto (APCCAS, 2006)

A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding. - Shen Li; Takeshi Ikenaga; Hideki Takeda; Masataka Matsui; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding. - Shen Li; Lingfeng Li; Takeshi Ikenaga; Shunichi Ishiwata; Masataka Matsui; Satoshi Goto (IEICE Trans. Inf. Syst., 2007)