A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. - Masato Iwabuchi; Masami Usami; Masamori Kashiyama; Takashi Oomori; Shigeharu Murata; Toshiro Hiramoto; Takashi Hashimoto; Yasuhiro Nakajima (IEEE J. Solid State Circuits, 1994)

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation. - Mikako Miyama; Goichi Yokomizo; Masato Iwabuchi; Masami Kinoshita (ASP-DAC, 1995)

A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design. - Masato Iwabuchi; Noboru Sakamoto; Yasushi Sekine; Takashi Omachi (ISPD, 1999)