Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card. - Masato Matsubayashi; Akashi Satoh (GCCE, 2015)

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit. - Masato Matsubayashi; Akashi Satoh; Jun Ishii (GCCE, 2016)

Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs. - Yu Nomata; Masato Matsubayashi; Kohei Sawada; Akashi Satoh (GCCE, 2016)

Security evaluation of cryptographic modules against side-channel attack using a biased data set. - Masato Matsubayashi; Hendra Guntur; Akashi Satoh (GCCE, 2017)