A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture. - Masato Matsumiya; Shoichiro Kawashima; Makoto Sakata; Masahiko Ookura; Toru Miyabo; Tom Koga; Kazuo Itabashi; Kazuhiro Mizutani; Hiroshi Shimada; Noriyuki Suzuki (IEEE J. Solid State Circuits, 1992)

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line. - Satoshi Eto; Masato Matsumiya; Masato Takita; Yuki Ishii; Toshikazu Nakamura; Kuninori Kawabata; Hideki Kano; Ayako Kitamoto; Toshimi Ikeda; Toru Koga; Mitsuhiro Higashiho; Yuji Serizawa; et al. (IEEE J. Solid State Circuits, 1998)