A 40-Mpixel/s bit block transfer graphics processor. - Masahiko Sumi; Shigeru Tanaka; Naoyuki Kai; Yuichi Miyazawa; Masato Nagamatsu; Tsutomu Minagawa; Ichiro Nagashima; Tsuneo Hamai; Junji Mori; Tatsuo Noguchi (IEEE J. Solid State Circuits, 1989)

A 15-ns 32*32-b CMOS multiplier with an improved parallel structure. - Masato Nagamatsu; Shigeru Tanaka; Junji Mori; Katsusi Hirano; Tatsuo Noguchi; Kazuhisa Hatanaka (IEEE J. Solid State Circuits, 1990)

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. - Junji Mori; Masato Nagamatsu; Masashi Hirano; Shigeru Tanaka; Makoto Noda; Yoshiaki Toyoshima; Kazuhiro Hashimoto; Hiroyuki Hayashida; Kenji Maeguchi (IEEE J. Solid State Circuits, 1991)

A 320 MFLOPS CMOS floating-point processing unit for superscalar processors. - Nobuhiro Ide; Hiroto Fukuhisa; Yoshihisa Kondo; Takeshi Yoshida; Masato Nagamatsu; Junji Mori; Itaru Yamazaki; Kiyoyi Ueno (IEEE J. Solid State Circuits, 1993)

A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder. - Masakazu Suzuoki; Ken Kutaragi; Toshiyuki Hiroi; Hidetaka Magoshi; Shin'ichi Okamoto; Masaaki Oka; Akio Ohba; Yasuyuki Yamamoto; Makoto Furuhashi; Masayoshi Tanaka; Teiji Yutaka; Toyoshi Okada; et al. (IEEE J. Solid State Circuits, 1999)

Importance of CAD tools and methodology in high speed CPU design: invited talk. - Haruyuki Tago; Kazuhiro Hashimoto; Nobuyuki Ikumi; Masato Nagamatsu; Masakazu Suzuoki; Yasuyuki Yamamoto (ASP-DAC, 2000)

CPU for PlayStation 2. - Haruyuki Tago; Kazuhiro Hashimoto; Nobuyuki Ikumi; Masato Nagamatsu; Masakazu Suzuoki; Yasuyuki Yamamoto (DATE, 2001)

A 3.96μm, 124dB Dynamic Range, 6.2mW Stacked Digital Pixel Sensor with Monochrome and Near-Infrared Dual-Channel Global Shutter Capture. - Song Chen; Chiao Liu; Lyle Bainbridge; Qing Chao; Ramakrishna Chilukuri; Wei Gao; Andrew P. Hammond; Tsung-Hsun Tsai; Ken Miyauchi; Isao Takayanagi; Masato Nagamatsu; Hirofumi Abe; et al. (VLSI Technology and Circuits, 2023)

6.4 A 400×400 3.24µm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor. - Tsung-Hsun Tsai; Kwuang-Han Chang; Andrew Berkovich; Raffaele Capoccia; Song Chen; Zhao Wang; Chiao Liu; Yi-Hsuan Lin; Sheng-Yeh Lai; Hao-Ming Hsu; Hirofumi Abe; Kazuya Mori; et al. (ISSCC, 2025)

A 3.96-μm, 124-dB Dynamic-Range, Digital-Pixel Sensor With Triple- and Single-Quantization Operations for Monochrome and Near-Infrared Dual-Channel Global Shutter Operation. - Ken Miyauchi; Masayuki Uno; Toshiyuki Isozaki; Hideyuki Fukuhara; Kazuya Mori; Hirofumi Abe; Masato Nagamatsu; Rimon Ikeno; Isao Takayanagi; Hsin-Li Chen; Chih-Hao Lin; Wen-Chien Fu; et al. (IEEE J. Solid State Circuits, 2025)