An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit. - Tomio Sato; Masato Sakate; H. Okada; T. Sukemura; Gensuke Goto (IEEE J. Solid State Circuits, 1992)

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. - Hajime Kubosawa; Naoshi Higaki; Satoshi Ando; Hiromasa Takahashi; Yoshimi Asada; Hideaki Anbutsu; Tomio Sato; Masato Sakate; Atsuhiro Suga; Michihide Kimura; Hideo Miyake; Hiroshi Okano; et al. (IEEE J. Solid State Circuits, 1999)