Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. - Masato Sumiyoshi; Takashi Midorikawa; Yasuki Tanabe; Hideharu Amano (PDCS, 2004)

A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. - Takahisa Wada; Shunichi Ishiwata; Katsuyuki Kimura; Keiri Nakanishi; Masato Sumiyoshi; Takashi Miyamori; Masaki Nakagawa (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. - Yasuki Tanabe; Masato Sumiyoshi; Manabu Nishiyama; Itaru Yamazaki; Shinsuke Fujii; Katsuyuki Kimura; Takuma Aoyama; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2012)