Physically aware high level synthesis design flow. - Masato Tatsuoka; Ryosuke Watanabe; Tatsushi Otsuka; Takashi Hasegawa; Qiang Zhu 005; Ryosuke Okamura; Xingri Li; Tsuyoshi Takabatake (DAC, 2015)

High quality IP design using high-level synthesis design flow. - Qiang Zhu 005; Masato Tatsuoka (ASP-DAC, 2016)

Wire congestion aware high level synthesis flow with source code compiler. - Masato Tatsuoka; Mineo Kaneko (ICICDT, 2018)

Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models. - Shogo Semba; Hiroshi Saito; Masato Tatsuoka; Katsuya Fujimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

High Level Congestion Detection from C/C++ Source Code for High Level Synthesis. - Masato Tatsuoka; Mineo Kaneko (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)