A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. - Yuji Yokoyama; Nobutaka Itoh; Masatoshi Hasegawa; Masahiro Katayama; Hiroshi Akasaki; Masayuki Kaneda; Toshitsugu Ueda; Yousuke Tanaka; Eiji Yamasaki; Masaya Todokoro; Keinosuke Toriyama; Hiroshi Miki; et al. (IEEE J. Solid State Circuits, 2001)

Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI. - Masaji Kume; Katsutoshi Uehara; Minoru Itakura; Hideo Sawamoto; Toru Kobayashi; Masatoshi Hasegawa; Hideki Hayashi (ITC, 2004)

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. - Takashi Kawamoto; Takayasu Norimatsu; Kenji Kogo; Fumio Yuki; Norio Nakajima; Masatoshi Tsuge; Tatsunori Usugi; Tomofumi Hokari; Hideki Koba; Takemasa Komori; Junya Nasu; Tsuneo Kawamata; et al. (ISSCC, 2015)

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. - Takayasu Norimatsu; Takashi Kawamoto; Kenji Kogo; Naohiro Kohmu; Fumio Yuki; Norio Nakajima; Takashi Muto; Junya Nasu; Takemasa Komori; Hideki Koba; Tatsunori Usugi; Tomofumi Hokari; et al. (ISSCC, 2016)