A CMOS multichannel 10-Gb/s transceiver. - Hideki Takauchi; Hirotaka Tamura; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takaya Chiba; Hideaki Anbutsu; Hisakatsu Yamaguchi; Toshihiko Mori; Motomu Takatsu; Kohtaroh Gotoh; Toshiaki Sakai; et al. (IEEE J. Solid State Circuits, 2003)

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. - Hirohito Higashi; Syunitirou Masaki; Masaya Kibune; Satoshi Matsubara; Takaya Chiba; Yoshiyasu Doi; Hisakatsu Yamaguchi; Hideki Takauchi; Hideki Ishida; Kohtaroh Gotoh; Hirotaka Tamura (IEEE J. Solid State Circuits, 2005)

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique. - Yusuke Okaniwa; Hirotaka Tamura; Masaya Kibune; Daisuke Yamazaki; Tsz-Shing Cheung; Junji Ogawa; Nestoras Tzartzanis; William W. Walker; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS. - Yasumoto Tomita; Masaya Kibune; Junji Ogawa; William W. Walker; Hirotaka Tamura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. - Yasumoto Tomita; Hirotaka Tamura; Masaya Kibune; Junji Ogawa; Kohtaroh Gotoh; Tadahiro Kuroda (ISSCC, 2006)

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies. - Hirotaka Tamura; Masaya Kibune; Hisakatsu Yamaguchi; Kouichi Kanda; Kohtaroh Gotoh; Hideki Ishida; Junji Ogawa (IEICE Trans. Electron., 2006)

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS. - Yasumoto Tomita; Hirotaka Tamura; Masaya Kibune; Junji Ogawa; Kohtaroh Gotoh; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (ISSCC, 2009)

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (IEEE J. Solid State Circuits, 2009)

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers. - Tina Tahmoureszadeh; Siamak Sarvari; Ali Sheikholeslami; Hirotaka Tamura; Yasumoto Tomita; Masaya Kibune (CICC, 2010)

A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. - Oleksiy Tyshchenko; Ali Sheikholeslami; Hirotaka Tamura; Yasumoto Tomita; Hisakatsu Yamaguchi; Masaya Kibune; Takuji Yamamoto (ISSCC, 2010)

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. - Hisakatsu Yamaguchi; Hirotaka Tamura; Yoshiyasu Doi; Yasumoto Tomita; Takayuki Hamada; Masaya Kibune; Shuhei Ohmoto; Keita Tateishi; Oleksiy Tyshchenko; Ali Sheikholeslami; Tomokazu Higuchi; Junji Ogawa; et al. (ISSCC, 2010)

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. - Yanfei Chen; Xiaolei Zhu 002; Hirotaka Tamura; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Junji Ogawa; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. - Xiaolei Zhu 002; Yanfei Chen; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Hirotaka Tamura; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. - Oleksiy Tyshchenko; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune; Hisakatsu Yamaguchi; Junji Ogawa (IEEE J. Solid State Circuits, 2010)

A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. - Behrooz Abiri; Ravi Shivnaraine; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune (ISSCC, 2011)

A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. - Behrooz Abiri; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune (ISSCC, 2011)

A pattern-guided adaptive equalizer in 65nm CMOS. - Shayan Shahramian; Clifford Ting; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune (ISSCC, 2011)

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS. - Behrooz Abiri; Ali Sheikholeslami; Hirotaka Tamura; Masaya Kibune (IEEE J. Solid State Circuits, 2011)

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection. - Mohammad Sadegh Jalali; Ravi Shivnaraine; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (CICC, 2013)

A Blind Baud-Rate ADC-Based CDR. - Clifford Ting; Joshua Liang; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (IEEE J. Solid State Circuits, 2013)

A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE. - Clifford Ting; Mohammad Sadegh Jalali; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (CICC, 2014)

On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. - Joshua Liang; Mohammad Sadegh Jalali; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (VLSIC, 2014)

An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset". - Ravi Shivnaraine; Mohammad Sadegh Jalali; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. - Yanfei Chen; Masaya Kibune; Asako Toda; Akinori Hayakawa; Tomoyuki Akiyama; Shigeaki Sekiguchi; Hiroji Ebe; Nobuhiro Imaizumi; Tomoyuki Akahoshi; Suguru Akiyama; Shinsuke Tanaka; Takasi Simoyama; et al. (ISSCC, 2015)

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects. - Akinori Hayakawa; Masaya Kibune; Asako Toda; Shinsuke Tanaka; Takasi Simoyama; Yanfei Chen; Tomoyuki Akiyama; Shigekazu Okumura; Takeshi Baba; Tomoyuki Akahoshi; Seiji Ueno; Kazunori Maruyama; et al. (OFC, 2015)

A Reference-Less Single-Loop Half-Rate Binary CDR. - Mohammad Sadegh Jalali; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (IEEE J. Solid State Circuits, 2015)

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs. - Joshua Liang; Mohammad Sadegh Jalali; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (IEEE J. Solid State Circuits, 2015)

A 3x blind ADC-based CDR for a 20 dB loss channel. - Mohammad Sadegh Jalali; Clifford Ting; Joshua Liang; Ali Sheikholeslami; Masaya Kibune; Hirotaka Tamura (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Efficient Learning Algorithm Using Compact Data Representation in Neural Networks. - Masaya Kibune; Michael G. Lee (ICONIP (2), 2017)