The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time. - Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2007)

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing. - Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof. - Kaziiya Kojima; Yasuhiro Toriyama; Toru Taniguchi; Masaya Miyahara; Akira Matsuzawa (ICECS, 2009)

An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques. - Daehwa Paik; Yusuke Asada; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. - Daehwa Paik; Masaya Miyahara; Akira Matsuzawa (ASICON, 2011)

A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. - James Lin; Masaya Miyahara; Akira Matsuzawa (ISCAS, 2011)

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (ISSCC, 2012)

A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching. - Hong Phuc Ninh; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2012)

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator. - Daehwa Paik; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. - James Lin; Daehwa Paik; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2013)

A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. - Zule Xu; Masaya Miyahara; Akira Matsuzawa (NEWCAS, 2013)

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. - Hyunui Lee; Yusuke Asada; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers. - Hyunui Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier. - Hyunui Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs. - Fei Li; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs. - Fei Li; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells. - Masao Takayama; Shiro Dosho; Noriaki Takeda; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (IEEE J. Solid State Circuits, 2013)

A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. - Wei Deng 001; Ahmed Musa; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ASP-DAC, 2014)

A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. - James Lin; Zule Xu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2014)

Radio receiver front-end using time-based all-digital ADC (TAD). - Tomohito Terasawa; Yuji Kamiya; Hiroyuki Kawashima; Kenichiro Imai; Masanobu Suzuki; Takamoto Watanabe; Nobuyuki Taguchi; Manabu Sawada; Yu Hou; Yoshiyuki Hirooka; Hong Phuc Ninh; Masaya Miyahara; et al. (ICECS, 2014)

All-digital 0.016mm2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS. - Takamoto Watanabe; Yu Hou; Masaya Miyahara; Akira Matsuzawa (ICECS, 2014)

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. - Masaya Miyahara; Ibuki Mano; Masaaki Nakayama; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2014)

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. - Kenichi Okada 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Yasuaki Takeuchi; Tatsuya Yamaguchi; Ahmed Musa; Rui Wu 001; et al. (ISSCC, 2014)

Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator. - Jeonghoon Han; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2014)

An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique. - James Lin; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A 7-bit 1-GS/s Flash ADC with Background Calibration. - Sanroku Tsukamoto; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2014)

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. - Ahmed Musa; Wei Deng 001; Teerachot Siriburanon; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2014)

A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (ASICON, 2015)

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. - Zule Xu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2015)

A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2015)

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ISSCC, 2015)

19.5 An HCI-healing 60GHz CMOS transceiver. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; Yasuaki Takeuchi; Tatsuya Yamaguchi; et al. (ISSCC, 2015)

An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. - Yu Hou; Takamoto Watanabe; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. - Tohru Kaneko; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2015)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. - James Lin; Daehwa Paik; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. - James Lin; Ibuki Mano; Masaya Miyahara; Akira Matsuzawa (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 2nd order fully-passive noise-shaping SAR ADC with embedded passive gain. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2016)

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. - Rui Wu 001; Jian Pang; Yuuki Seo; Kento Kimura; Seitaro Kawai; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Yasuaki Takeuchi; Tatsuya Yamaguchi; Ahmed Musa; et al. (A-SSCC, 2016)

A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2016)

A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2016)

A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. - Tohru Kaneko; Yuya Kimura; Koji Hirose; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2016)

A 2 GHz 3.1 mW type-I digital ring-based PLL. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (ISCAS, 2016)

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. - Rui Wu 001; Seitaro Kawai; Yuuki Seo; Nurul Fajri; Kento Kimura; Shinji Sato; Satoshi Kondo; Tomohiro Ueno; Teerachot Siriburanon; Shoutarou Maki; Bangan Liu; Yun Wang 008; et al. (ISSCC, 2016)

A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC. - Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology. - Yu Hou; Zhijie Chen; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. - Mitsutoshi Sugawara; Kenji Mori; Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2016)

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. - Teerachot Siriburanon; Satoshi Kondo; Kento Kimura; Tomohiro Ueno; Satoshi Kawashima; Tohru Kaneko; Wei Deng 001; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. - Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers. - Lilan Yu; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. - Akira Matsuzawa; Masaya Miyahara (ASICON, 2017)

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (ASICON, 2017)

A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2017)

An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. - Masaya Miyahara; Akira Matsuzawa (CICC, 2017)

A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (ESSCIRC, 2017)

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (ISSCC, 2017)

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. - Tohru Kaneko; Yuya Kimura; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. - Rui Wu 001; Ryo Minami; Yuuki Tsukui; Seitaro Kawai; Yuuki Seo; Shinji Sato; Kento Kimura; Satoshi Kondo; Tomohiro Ueno; Nurul Fajri; Shoutarou Maki; Noriaki Nagashima; et al. (IEEE J. Solid State Circuits, 2017)

A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. - Masaya Miyahara; Yukiya Endo; Kenichi Okada 001; Akira Matsuzawa (VLSI Circuits, 2018)

SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier. - Akira Matsuzawa; Masaya Miyahara (IEICE Electron. Express, 2018)

A 7GS/s Complete-DDFS-Solution in 65nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. - Tohru Kaneko; Yuya Kimura; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2018)

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS. - Abdel Martinez Alonso; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2018)

An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. - Yuji Yano; Seiya Yoshida; Shintaro Izumi; Hiroshi Kawaguchi 001; Tetsuya Hirose; Masaya Miyahara; Teruki Someya; Kenichi Okada 001; Ippei Akita; Yoshihiko Kurui; Hideyuki Tomizawa; Masahiko Yoshimoto (A-SSCC, 2019)

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2019)

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. - Jian Pang; Shotaro Maki; Seitarou Kawai; Noriaki Nagashima; Yuuki Seo; Masato Dome; Hisashi Kato; Makihiko Katsuragi; Kento Kimura; Satoshi Kondo; Yuki Terashima; Hanli Liu; et al. (IEEE J. Solid State Circuits, 2019)

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Jian Pang; Hanli Liu; Masaya Miyahara; et al. (IEEE J. Solid State Circuits, 2021)

A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications. - Masaya Miyahara; Zule Xu; Takehito Ishii; Noritoshi Kimura (IEICE Trans. Electron., 2023)