Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. - Shen Lin; Makoto Nagata; Kenji Shimazaki; Kazuhiro Satoh; Masaya Sumita; Hiroyuki Tsujikawa; Andrew T. Yang (CICC, 2004)

High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar. - Masaya Sumita (ISLPED, 2005)

Mixed body bias techniques with fixed Vt and Ids generation circuits. - Masaya Sumita; Shiro Sakiyama; Masayoshi Kinoshita; Yuta Araki; Yuichiro Ikeda; Kohei Fukuoka (IEEE J. Solid State Circuits, 2005)

A 14: 1 dynamic MUX FF with select activity detection. - Masaya Sumita; T. Wada (ISSCC, 2006)

Multi-Ported Register File for Reducing the Impact of PVT Variation. - Yuuichirou Ikeda; Masaya Sumita; Makoto Nagata (IEICE Trans. Electron., 2006)

Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier". - Masaitsu Nakajima; Takao Yamamoto; Masayuki Yamasaki; Tetsu Hosoki; Masaya Sumita (ASP-DAC, 2007)

Design of "green" high-performance processor circuits. - Tobias Noll; Raney Southerland; Vladimir Stojanovic; Sonia Leon; Lew Chua-Eoan; Alice Wang; Byeong-Gyu Nam; Masaya Sumita (ISSCC, 2011)

Session 28 overview: Adaptive and low-power circuits: Energy-efficient digital subcommittee. - Michael Phan; Masaya Sumita (ISSCC, 2012)

Session 24 overview: Energy-aware digital design. - Wim Dehaene; Masaya Sumita (ISSCC, 2013)