Scalable GA processor architecture and its implementation of processor-element. - Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi (ICASSP, 2002)

VLSI processor architecture for real-time GA processing and PE-VLSI design. - Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi (ISCAS (3), 2004)

Performance driven placement technique based on collaboration of software and hardware. - Masaya Yoshikawa; Hidekazu Terai (Congress on Evolutionary Computation, 2005)

Hybrid genetic algorithm engine for high-speed floorplanning. - Masaya Yoshikawa; Hidekazu Terai (ECCTD, 2005)

A Hierarchical Parallel Placement Technique based on Genetic Algorithm. - Masaya Yoshikawa; Hidekazu Terai (ISDA, 2005)

Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. - Masaya Yoshikawa; Hidekazu Terai (SERA, 2005)

Co-evolutionary robotics using two kinds of neural networks. - Masaya Yoshikawa; Hidekazu Terai (CAINE, 2006)

Immune Algorithm Processor. - Masaya Yoshikawa; Masahiro Fukui; Hidekazu Terai (CATA, 2006)

Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. - Masaya Yoshikawa; Hidekazu Terai (SERA, 2006)

Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. - Masaya Yoshikawa; Hidekazu Terai (J. Adv. Comput. Intell. Intell. Informatics, 2006)

Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. - Akihiro Nakamura; Masahide Kawaharazaki; Masaya Yoshikawa; Takeshi Fujino (CICC, 2007)

Architecture for high-speed Ant Colony Optimization. - Masaya Yoshikawa; Hidekazu Terai (IRI, 2007)

The new DFM approach based on a genetic algorithm. - Masaya Yoshikawa; Hidekazu Terai (Artif. Life Robotics, 2007)

Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption. - Masaya Yoshikawa; Hidekazu Terai (J. Adv. Comput. Intell. Intell. Informatics, 2007)

Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. - Masaya Yoshikawa; Hidekazu Terai (GEM, 2008)

Route selection algorithm based on integer operation Ant Colony Optimization. - Masaya Yoshikawa; Hidekazu Terai (IRI, 2008)

Hybrid Architecture of Genetic Algorithm and Simulated Annealing. - Masaya Yoshikawa; Hironori Yamauchi; Hidekazu Terai (Eng. Lett., 2008)

Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. - Akihiro Nakamura; Masahide Kawarasaki; Kouta Ishibashi; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Electron., 2008)

Car Navigation System Based on Hybrid Genetic Algorithm. - Masaya Yoshikawa; Hidekazu Terai (CSIE (5), 2009)

OX Hardware Engine for High Speed Character Inheritance. - Masaya Yoshikawa; Hidekazu Terai (GEM, 2009)

Adaptive Immune Algorithm Considering Intensification and Diversification. - Masaya Yoshikawa; Akira Naruse; Shinsuke Souboku (IRI, 2009)

An Efficient Hardware Accelerator for Power Grid Simulation. - Taiki Hashizume; Hisako Sugano; Shinichi Nishizawa; Masaya Yoshikawa; Masahiro Fukui (ISCAS, 2009)

Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. - Masaya Yoshikawa; Hidekazu Terai (ITNG, 2009)

Placement Tool Dedicated for a Via-programmable Logic Device VPEX. - Masaya Yoshikawa; Yuichi Kokusyo; Takeshi Fujino (CAINE, 2010)

Hybrid Ant Colony Optimization for intensification and diversification. - Masaya Yoshikawa; Shimohigashi Yoshiaki (IRI, 2010)

A power grid optimization algorithm considering via reliability. - Masahiro Fukui; Haruo Miki; Masaya Yoshikawa; Shuji Tsukiyama (ECCTD, 2011)

Efficient Random Number for the Masking Method against DPA Attacks. - Masaya Yoshikawa; Y. Kojima (ICSEng, 2011)

Multi-rounds masking method against DPA attacks. - Masaya Yoshikawa; M. Sugiyama (IRI, 2011)

Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. - Masaya Yoshikawa; Takeshi Fujino (Int. J. Comput. Their Appl., 2011)

Multiplexing aware arbiter physical unclonable function. - Masaya Yoshikawa; Akira Naruse (IRI, 2012)

Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. - Ryohei Hori; Tatsuya Kitamori; Taisuke Ueoka; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. - Ryohei Hori; Taisuke Ueoka; Taku Otani; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. - Mitsuru Shiozaki; Kota Furuhashi; Takahiko Murayama; Akitaka Fukushima; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Electron., 2012)

Hardware Trojan for security LSI. - Masaya Yoshikawa; R. Satoh; Takeshi Kumaki (ICCE, 2013)

Platform for Verification of Electromagnetic Analysis Attacks against Cryptographic Circuits. - Masaya Yoshikawa; Toshiya Asai (ITNG, 2013)

Cipher-destroying and secret-key-emitting hardware Trojan against AES core. - Takeshi Kumaki; Masaya Yoshikawa; Takeshi Fujino (MWSCAS, 2013)

The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. - Ryohei Hori; Taisuke Ueoka; Taku Otani; Masaya Yoshikawa; Takeshi Fujino (VLSI-DAT, 2013)

Study of threat for automotive embedded system by Trojan virus. - Kohei Nohara; Kensaku Asahi; Masaya Yoshikawa (GCCE, 2014)

PUF ID generation method for modeling attacks. - Yusuke Nozaki; Kensaku Asahi; Masaya Yoshikawa (GCCE, 2014)

Vulnerability evaluation of multiplexing PUF for SVM attacks. - S. Kiryu; Kensaku Asahi; Masaya Yoshikawa (ICSEng, 2014)

Error value driven fault analysis attack. - Masaya Yoshikawa; Hikaru Goto; Kensaku Asahi (SNPD, 2014)

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. - Mitsuru Shiozaki; Kousuke Ogawa; Kota Furuhashi; Takahiko Murayama; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Secure in-vehicle systems against Trojan attacks. - Masaya Yoshikawa; Kyota Sugioka; Yusuke Nozaki; Kensaku Asahi (ICIS, 2015)

Detection technique for hardware Trojans using machine learning in frequency domain. - Takato Iwase; Yusuke Nozaki; Masaya Yoshikawa; Takeshi Kumaki (GCCE, 2015)

Hardware Trojan for ultra lightweight block cipher Piccolo. - Kohei Nohara; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2015)

Statistical fault analysis for a lightweight block cipher TWINE. - Yusuke Nozaki; Kensaku Asahi; Masaya Yoshikawa (GCCE, 2015)

Design and LSI prototyping of security module with hardware trojan. - Masaya Yoshikawa; Takuya Tsukadaira; Takeshi Kumaki (ICCE, 2015)

Power analysis for clock fluctuation LSI. - Yusuke Nozaki; Toshiya Asai; Kensaku Asahi; Masaya Yoshikawa (SNPD, 2015)

Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems. - Masaya Yoshikawa; Yusuke Nozaki; Toshiya Asai; Kensaku Asahi (VTC Fall, 2015)

Secure in-vehicle Systems using Authentication. - Masaya Yoshikawa; Kyota Sugioka; Yusuke Nozaki; Kensaku Asahi (Int. J. Networked Distributed Comput., 2015)

Vulnerability Evaluation Accelerator for Lightweight Ciphers. - Masaya Yoshikawa; Yusuke Nozaki; Kensaku Asahi (BigDataSecurity/HPSC/IDS, 2016)

Multiple Rounds Aware Power Analysis Attack for a Lightweight Cipher SIMECK. - Masaya Yoshikawa; Yusuke Nozaki; Kensaku Asahi (BigDataService, 2016)

Deep learning attack for physical unclonable function. - Yoshiya Ikezaki; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2016)

Hardware Trojan for an authenticated encryption Minalpher. - Yusuke Nozaki; Yoshiya Ikezaki; Masaya Yoshikawa (GCCE, 2016)

Two Stage Fault Analysis against a Falsification Detection Cipher Minalpher. - Masaya Yoshikawa; Yusuke Nozaki (SmartCloud, 2016)

Hierarchical power analysis attack for falsification detection cipher. - Masaya Yoshikawa; Yusuke Nozaki (CCWC, 2017)

FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF. - Yoshiya Ikezaki; Yusuke Nozaki; Hideki Nagata; Masaya Yoshikawa (GCCE, 2017)

Power analysis for a lightweight authenticated encryption SIMON-JAMBU. - Yusuke Nozaki; Yoshiya Ikezaki; Hideki Nagata; Masaya Yoshikawa (GCCE, 2017)

Tamper resistance evaluation of PUF implementation against machine learning attack. - Yusuke Nozaki; Masaya Yoshikawa (ICBEA, 2017)

Statistical fault analysis for a lightweight cipher midori. - Yusuke Nozaki; Masaya Yoshikawa (ICIA, 2017)

Helper Data Aware Cloning Method for Physical Unclonable Function. - Masaya Yoshikawa; Yusuke Nozaki (SmartCloud, 2017)

Electromagnetic analysis method for ultra low power cipher Midori. - Masaya Yoshikawa; Yusuke Nozaki (UEMCON, 2017)

Feature Extraction Driven Modeling Attack Against Double Arbiter PUF and Its Evaluation. - Susumu Matsumi; Yusuke Nozaki; Masaya Yoshikawa (AICCC, 2018)

Security Evaluation of a Lightweight Cipher SPECK against Round Addition DFA. - Yusuke Nozaki; Masaya Yoshikawa (AICCC, 2018)

Shuffling Based Side-Channel Countermeasure for Energy Harvester. - Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2018)

Feasibility Evaluation of Neural Network Physical Unclonable Function. - Kazuya Shibagaki; Taichi Umeda; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2018)

Lethal Genes Aware Genetic Programming Analysis for RO PUF. - Taichi Umeda; Kazuya Shibagaki; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2018)

EM based machine learning attack for XOR arbiter PUF. - Yusuke Nozaki; Masaya Yoshikawa (ICMLSC, 2018)

Lightweight Cipher Aware Countermeasure Using Random Number Masks and Its Evaluation. - Masaya Yoshikawa; Yusuke Nozaki (ICVISP, 2018)

Implementation of Searchable Encryption System with Dedicated Hardware and its Evaluation. - Masaya Yoshikawa; Yoshiya Ikezaki; Yusuke Nozaki (UEMCON, 2018)

Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller. - Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (IWCIA, 2019)

Performance Evaluation of CAESAR Authenticated Encryption on SROS2. - Shu Takemoto; Kanata Nishida; Yusuke Nozaki; Masaya Yoshikawa; Shinya Honda; Ryo Kurachi (AICCC, 2019)

Countermeasure of Lightweight Physical Unclonable Function Against Side-Channel Attack. - Yusuke Nozaki; Masaya Yoshikawa (CCC, 2019)

Secret Sharing Schemes Based Secure Authentication for Physical Unclonable Function. - Yusuke Nozaki; Masaya Yoshikawa (ICCCS, 2019)

Side-Channel Analysis for Searchable Encryption System and its Security Evaluation. - Masaya Yoshikawa; Yusuke Nozaki (CSE/EUC, 2019)

Security Evaluation of Counter Synchronization Method for CAN Against DoS Attack. - Kanata Nishida; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2019)

Quantitative Performance Evaluation of PL PUF and RO PUF with ASIC Implementation. - Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2019)

Evaluation of the Hiding-Countermeasure PRINCE Using Differential Power Analysis. - Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2019)

Scalability and Performance Evaluation of GA Based Modeling Analysis for RO PUF. - Taichi Umeda; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2019)

Side-Channel Resistance Evaluation Method using Statistical Tests for Physical Unclonable Function. - Yusuke Nozaki; Masaya Yoshikawa (ICAIIC, 2019)

Security Evaluation of Ring Oscillator PUF Against Genetic Algorithm Based Modeling Attack. - Yusuke Nozaki; Masaya Yoshikawa (IMIS, 2019)

Unrolled PRINCE Cipher based Glitch Physically Unclonable Function. - Yusuke Nozaki; Masaya Yoshikawa (ICISS, 2020)

Tamper Resistance Evaluation of TWINE Implemented on 8-bit Microcontroller. - Yusuke Nozaki; Masaya Yoshikawa (ICSIM, 2020)

Hardware Trojan for Lightweight Cryptoraphy Elephant. - Shu Takemoto; Yoshiya Ikezaki; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2021)

Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. - Yusuke Nozaki; Shu Takemoto; Yoshiya Ikezaki; Masaya Yoshikawa (ISDCS, 2021)

Neural Network Based Glitch Physically Unclonable Function. - Yusuke Nozaki; Masaya Yoshikawa (UEMCON, 2021)

Authenticated Encryption based Secure In-vehicle System against DoS Attacks. - Daichi Hirose; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (GCCE, 2022)

AI Hardware Oriented Trojan Detection Architecture. - Shu Takemoto; Yoshiya Ikezaki; Yusuke Nozaki; Masaya Yoshikawa (ICECC, 2022)

Hamming Weight aware Fault Analysis for Lightweight Cryptography TWINE. - Yusuke Nozaki; Shu Takemoto; Masaya Yoshikawa (CCIOT, 2023)

Security Evaluation of Glitch Based Authentication Function for Edge AI. - Yusuke Nozaki; Shu Takemoto; Yoshiya Ikezaki; Masaya Yoshikawa (GCCE, 2023)

Deep Learning Based Side-Channel Analysis for Lightweight Cipher PRESENT. - Yusuke Nozaki; Shu Takemoto; Yoshiya Ikezaki; Masaya Yoshikawa (ICCAE, 2023)

Machine Learning Based Power Analysis for Simon with Secure Mechanism. - Shu Takemoto; Yoshiya Ikezaki; Yusuke Nozaki; Masaya Yoshikawa (ICCAE, 2023)

Explainable AI based Adversarial Examples and its Evaluation. - Ryo Kumagai; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ICECC, 2023)

Implementation and Evaluation of the Lightweight Cipher SPARKLE. - Masato Sato; Yusuke Nozaki; Masaya Yoshikawa (ICECC, 2023)

Tamper Resistance Evaluation of Midori128 against Differential Power Analysis. - Yusuke Nozaki; Shu Takemoto; Masaya Yoshikawa (ICKII, 2023)

Adversarial Examples for Field Programmable Gate Array based AI Module. - Yusuke Nozaki; Shu Takemoto; Masaya Yoshikawa (AICCC, 2024)

SuperSonic Glitch Physical Unclonable Function for Encryption and Device Authentication. - Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (AICCC, 2024)

Hue and Saturation oriented Imperceptible Adversarial Examples and their Evaluation. - Ryo Kumagai; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ITCC, 2024)

Error Correction Method for Lightweight Cipher PRINCE based Physically Unclonable Function. - Yusuke Nozaki; Shu Takemoto; Masaya Yoshikawa (ITCC, 2024)

Luminance Correction based Countermeasure against Adversarial Examples. - Takumi Tojo; Ryo Kumagai; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ITCC, 2024)

Quantitative Evaluation of Vulnerabilities in Adversarial Shadow Attack. - Chisei Ishida; Ryo Kumagai; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ICCAE, 2025)

Security Evaluation of Differentially Private Federated Learning Against Model Inversion Attacks. - Kohei Kanada; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ICCAE, 2025)

Quantization of Tiny MLP-Mixer and Its Evaluation. - Ryo Kumagai; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ICCAE, 2025)

Power Based Side-Channel Analysis for Lightweight Cipher Ltlbc. - Yusuke Nozaki; Shu Takemoto; Masaya Yoshikawa (ICCAE, 2025)

Parameter Free Countermeasure Against Adversarial Examples. - Takumi Tojo; Ryo Kumagai; Shu Takemoto; Yusuke Nozaki; Masaya Yoshikawa (ICCAE, 2025)