A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. - Kazuo Yano; Toshiaki Yamanaka; Takashi Nishida; Masayoshi Saito; Katsuhiro Shimohigashi; Akihiro Shimizu (IEEE J. Solid State Circuits, 1990)

Simple Modeling of an Abdomen of Pregnant Women and Its Application to SAR Estimation. - Hiroki Kawai; Koichi Ito 003; Masaharu Takahashi; Kazuyuki Saito; Takuya Ueda; Masayoshi Saito; Hisao Ito; Hisao Osada; Yoshio Koyanagi; Koichi Ogawa (IEICE Trans. Commun., 2006)