A VLSI chip set for a large-scale parallel inference machine: PIM/m. - Hirohisa Machida; Hideki Ando; Kenichi Yasuda; Kiyohiro Furutani; Yukihiro Yamashita; Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Masayoshi Sakao; Masao Nakaya (IEEE J. Solid State Circuits, 1993)

A 1.71-million transistor CMOS CPU chip with a testable cache architecture. - Yuichi Saito; Yukihiko Shimazu; Tom Shimizu; Kenji Shirai; Isao Fujioka; Yoshitetsu Nishiwaki; Junichi Hinata; Yoshiki Shimotsuma; Masayoshi Sakao (IEEE J. Solid State Circuits, 1993)

A high-density data-path generator with stretchable cells. - Yoshiki Tsujihashi; Hisashi Matsumoto; Hidekatsu Nishimaki; Atsushi Miyanishi; Hiroomi Nakao; Osamu Kitada; Shuhei Iwade; Shinpei Kayano; Masayoshi Sakao (IEEE J. Solid State Circuits, 1994)