Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Minoru Yamada; Akira Masaki (IJCNN, 1990)

A self-learning digital neural network using wafer-scale LSI. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Katsunari Shibata; Mitsuo Ooyama; Minoru Yamada; Takahiro Sakaguchi; Masashi Hashimoto (IEEE J. Solid State Circuits, 1993)

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory cell efficiency of 33%. - Yuji Yokoyama; Nybutaka Itoh; Masap Katayama; Kazumasa Takashima; Hiroshi Akasaki; Masayuki Kaneda; Toshitsugu Ueda; Yousuke Tanaka; Eiji Yamasaki; Masaya Todokoro; Keinosuke Toriyama; Hiroshi Miki; et al. (CICC, 2000)

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. - Yuji Yokoyama; Nobutaka Itoh; Masatoshi Hasegawa; Masahiro Katayama; Hiroshi Akasaki; Masayuki Kaneda; Toshitsugu Ueda; Yousuke Tanaka; Eiji Yamasaki; Masaya Todokoro; Keinosuke Toriyama; Hiroshi Miki; et al. (IEEE J. Solid State Circuits, 2001)

A Low-Power Write Driver for Hard Disk Drives. - Tatsuya Kawashimo; Hiroki Yamashita; Masayoshi Yagyu; Fumio Yuki (IEICE Trans. Electron., 2006)

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Masayoshi Yagyu; Ryo Nemoto; Takashi Takemoto; Tatsuya Saito; Norio Chujo; Keiichi Yamamoto; Hisaaki Kanai; Atsuhiro Hayashi (ISSCC, 2008)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)