A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features. - Masayuki Hiromoto; Kentaro Nakahara; Hiroki Sugano; Yukihiro Nakamura; Ryusuke Miyamoto (CVPR, 2007)

Coarse-grained dynamically reconfigurable architecture with flexible reliability. - Dawood Alnajiar; Younghun Ko; Takashi Imagawa; Hiroaki Konoura; Masayuki Hiromoto; Yukio Mitsuyama; Masanori Hashimoto; Hiroyuki Ochi; Takao Onoye (FPL, 2009)

Hot-Swapping architecture extension for mitigation of permanent functional unit faults. - Zoltan Endre Rakosi; Masayuki Hiromoto; Hiroyuki Ochi; Yukihiro Nakamura (FPL, 2009)

Hardware architecture for high-accuracy real-time pedestrian detection with CoHOG features. - Masayuki Hiromoto; Ryusuke Miyamoto (ICCV Workshops, 2009)

Cascade Classifier Using Divided CoHOG Features for Rapid Pedestrian Detection. - Masayuki Hiromoto; Ryusuke Miyamoto (ICVS, 2009)

Hardware Architecture for HOG Feature Extraction. - Ryoji Kadota; Hiroki Sugano; Masayuki Hiromoto; Hiroyuki Ochi; Ryusuke Miyamoto; Yukihiro Nakamura (IIH-MSP, 2009)

Dynamic rate control for media streaming in high-speed mobile networks. - Masayuki Hiromoto; Hiroshi Tsutsui; Hiroyuki Ochi; Tomoyuki Osano; Norihiro Ishikawa; Yukihiro Nakamura (WCNC, 2009)

An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. - Masayuki Hiromoto; Hiroyuki Ochi; Yukihiro Nakamura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features. - Masayuki Hiromoto; Hiroki Sugano; Ryusuke Miyamoto (IEEE Trans. Circuits Syst. Video Technol., 2009)

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (SoCC, 2010)

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. - Zoltán Endre Rákossy; Masayuki Hiromoto; Hiroshi Tsutsui; Takashi Sato 001; Yukihiro Nakamura; Hiroyuki Ochi (DATE, 2013)

Variability in device degradations: Statistical observation of NBTI for 3996 transistors. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ESSDERC, 2014)

Automation of Model Parameter Estimation for Random Telegraph Noise. - Hirofumi Shimizu; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2015)

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2015)

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. - Song Bian 001; Michihiro Shintani; Zheng Wang 020; Masayuki Hiromoto; Anupam Chattopadhyay; Takashi Sato 001 (ATS, 2016)

Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor. - Takayuki Ujiie; Masayuki Hiromoto; Takashi Sato 001 (CVPR Workshops, 2016)

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2016)

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. - Motoki Yoshinaga; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ISCAS, 2016)

Nonlinear delay-table approach for full-chip NBTI degradation prediction. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2016)

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. - Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Efficient circuit failure probability calculation along product lifetime considering device aging. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2017)

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. - Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2017)

SCAM: Secured content addressable memory based on homomorphic encryption. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2017)

Comparative study of path selection and objective function in replacing NBTI mitigation logic. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2017)

Identification and Application of Invariant Critical Paths under NBTI Degradation. - Song Bian 001; Shumpei Morita; Michihiro Shintani; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2018)

Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems. - Takayuki Ujiie; Masayuki Hiromoto; Takashi Sato 001 (CVPR Workshops, 2018)

DWE: decrypting learning with errors with errors. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2018)

Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection. - Yuya Fujita; Masayuki Hiromoto; Takashi Sato 001 (EMBC, 2018)

Enhancing the solution quality of hardware ising-model solver via parallel tempering. - Hidenori Gyoten; Masayuki Hiromoto; Takashi Sato 001 (ICCAD, 2018)

A study on NBTI-induced delay degradation considering stress frequency dependence. - Zuitoku Shin; Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2018)

Area Efficient Annealing Processor for Ising Model without Random Number Generator. - Hidenori Gyoten; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Inf. Syst., 2018)

MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator. - Masayuki Hiromoto; Motoki Yoshinaga; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update. - Satoshi Yamamori; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise. - Yuya Fujita; Masayuki Hiromoto; Takashi Sato 001 (IEEE Trans. Biomed. Eng., 2018)

Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks. - Yuki Tanaka; Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2019)

Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2019)

DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2019)

Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

GPU-based Ising computing for solving max-cut combinatorial optimization problems. - Chase Cook; Hengyang Zhao; Takashi Sato 001; Masayuki Hiromoto; Sheldon X.-D. Tan (Integr., 2019)

ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. - Song Bian 001; Tianchen Wang; Masayuki Hiromoto; Yiyu Shi 001; Takashi Sato 001 (CVPR, 2020)

SimpleZSL: Extremely Simple and Fast Zero-Shot Learning with Nearest Neighbor Classifiers. - Masayuki Hiromoto; Hisanao Akima; Teruo Ishihara; Takuji Yamamoto (IEICE Trans. Inf. Syst., 2022)

Improving Predicate Representation in Scene Graph Generation by Self-Supervised Learning. - So Hasegawa; Masayuki Hiromoto; Akira Nakagawa; Yuhei Umeda (WACV, 2023)