VLSI Architecture for an adaptive equalizer in ISDN line termination. - Masayuki Ishikawa; Tsuneo Tsukahara; Tadakatsu Kimura (ICASSP, 1986)

An adaptive line equalizer VLSI using digital signal processing. - Masayuki Ishikawa; Yukio Tanaka; Tadakatsu Kimura (IEEE J. Solid State Circuits, 1988)

An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H. - Masayuki Ishikawa; Tsuneo Tsukahara (IEEE J. Solid State Circuits, 1989)

A Framework for Automatic Improvement of Workflows to Meet Performance Goals. - Trent Jaeger; Atul Prakash 001; Masayuki Ishikawa (ICTAI, 1994)

A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator. - Tsuneo Tsukahara; Masayuki Ishikawa; Masahiro Muraguchi (IEEE J. Solid State Circuits, 1996)

A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication. - Akihiro Yamagishi; Masayuki Ishikawa; Tsuneo Tsukahara; Shigeru Date (IEEE J. Solid State Circuits, 1998)

Information Diffusion Approach to Cold-Start Problem. - Masayuki Ishikawa; Peter Géczy; Noriaki Izumi; Takeshi Morita 001; Takahira Yamaguchi (Web Intelligence/IAT Workshops, 2007)

Capturing Knowledge Worker Behavior Based on Information Diffusion Theory. - Masayuki Ishikawa; Peter Géczy; Noriaki Izumi; Takahira Yamaguchi (JCKBSE, 2008)

Long Tail Recommender Utilizing Information Diffusion Theory. - Masayuki Ishikawa; Peter Géczy; Noriaki Izumi; Takahira Yamaguchi (Web Intelligence, 2008)

On suitable pseudo-noise code for optical-wireless hierarchical CSK-MPPM system. - Masayuki Ishikawa; Hiromasa Habuchi (GCCE, 2017)

Norm-Regularized Token Compression in Vision Transformer Networks. - Masayuki Ishikawa; Ryuto Ishibashi; Lin Meng (ATAIT, 2024)