An image sensor with fast extraction of objects' positions - rough vision processor. - Akira Watanabe; Osamu Tooyama; Masayuki Miyama; Masahiko Yoshimoto; Junichi Akita (ICIP (2), 2001)

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. - Masayuki Miyama; Osamu Tooyama; N. Takamatsu; T. Kodake; K. Nakamura; A. Kato; Junichi Miyakoshi; K. Hashimoto; Shigenobu Komatsu; M. Yagi; Masao Morimoto; Kazuo Taki; et al. (CICC, 2002)

A sub-mW MPEG-4 motion estimation processor core for mobile video application. - Junichi Miyakoshi; Yuri Kuroda; Masayuki Miyama; Kosuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (CICC, 2003)

A sub-mW MPEG-4 motion estimation processor core for mobile video application. - Yuki Kuroda; Junichi Miyakoshi; Masayuki Miyama; Kousuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (ASP-DAC, 2004)

Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. - Kentaro Kawakami; Miwako Kanamori; Yasuhiro Morita; Jun Takemura; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. - Junichi Miyakoshi; Yuichiro Murachi; Koji Hamano; Tetsuro Matsuno; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Electron., 2005)

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. - Yuichiro Murachi; Koji Hamano; Tetsuro Matsuno; Junichi Miyakoshi; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. - Kentaro Kawakami; Miwako Kanamori; Yasuhiro Morita; Jun Takemura; Hideo Ohira; Masayuki Miyama; Masahiko Yoshimoto (Intell. Autom. Soft Comput., 2006)

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. - Noriyuki Minegishi; Junichi Miyakoshi; Yuki Kuroda; Tadayoshi Katagiri; Yuki Fukuyama; Ryo Yamamoto; Masayuki Miyama; Kousuke Imamura; Hideo Hashimoto; Masahiko Yoshimoto (IEICE Trans. Electron., 2006)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. - Junichi Miyakoshi; Yuichiro Murachi; Tetsuro Matsuno; Masaki Hamamoto; Takahiro Iinuma; Tomokazu Ishihara; Hiroshi Kawaguchi 001; Masayuki Miyama; Masahiko Yoshimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission. - Masayuki Miyama; Yuusuke Inoie; Takafumi Kasuga; Ryouichi Inada; Masashi Nakao; Yoshio Matsuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. - Yuichiro Murachi; Yuki Fukuyama; Ryo Yamamoto; Junichi Miyakoshi; Hiroshi Kawaguchi 001; Hajime Ishihara; Masayuki Miyama; Yoshio Matsuda; Masahiko Yoshimoto (IEICE Trans. Electron., 2008)

Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage. - Shunji Nakata; Takahito Kusumoto; Masayuki Miyama; Yoshio Matsuda (ISCAS, 2009)

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. - Shunji Nakata; Hirotsugu Suzuki; Ryota Honda; Takahito Kusumoto; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (ISCAS, 2010)

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. - Shunji Nakata; Shin'ichiro Mutoh; Hiroshi Makino; Masayuki Miyama; Yoshio Matsuda (IEICE Electron. Express, 2010)

A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications. - Katsumi Dosaka; Daisuke Ogawa; Takahito Kusumoto; Masayuki Miyama; Yoshio Matsuda (IEICE Trans. Electron., 2010)

A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation. - Yoshiki Yunbe; Masayuki Miyama; Yoshio Matsuda (IEICE Trans. Inf. Syst., 2010)

Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system. - Shunji Nakata; Masayuki Miyama; Yoshio Matsuda (IET Circuits Devices Syst., 2010)

Vehicle detection and tracking with affine motion segmentation in stereo video. - Masayuki Miyama; Yoshio Matsuda (ICSIPA, 2011)

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. - Hiroshi Makino; Shunji Nakata; Hirotsugu Suzuki; Shin'ichiro Mutoh; Masayuki Miyama; Tsutomu Yoshimura; Shuhei Iwade; Yoshio Matsuda (IET Circuits Devices Syst., 2012)

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. - Shunji Nakata; Ryota Honda; Hiroshi Makino; Shin'ichiro Mutoh; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. - Shunji Nakata; Hiroshi Makino; Ryota Honda; Masayuki Miyama; Yoshio Matsuda (J. Circuits Syst. Comput., 2014)

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. - Shunji Nakata; Hiroki Hanazono; Hiroshi Makino; Hiroki Morimura; Masayuki Miyama; Yoshio Matsuda (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fast stereo matching with super-pixels using one-way check and score filter. - Masayuki Miyama (ICCSCE, 2017)

HD 180 FPS FPGA Processor to Generate Depth Image with Clear Object Boundary. - Masayuki Miyama (ISDCS, 2019)

FPGA Implementation of 3-Bit Quantized Multi-Task CNN for Contour Detection and Disparity Estimation. - Masayuki Miyama (IEICE Trans. Inf. Syst., 2022)