A GHz MOS adaptive pipeline technique using MOS current-mode logic. - Masayuki Mizuno; Masakazu Yamashina; Koichiro Furuta; Hiroyuki Igura; Hitoshi Abiko; Kazuhiro Okabe; Atsuki Ono; Hachiro Yamada (IEEE J. Solid State Circuits, 1996)

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. - Tomofumi lima; Masayuki Mizuno; Tadahiko Horiuchi; Masakazu Yamashina (IEEE J. Solid State Circuits, 1996)

An MPEG-2 encoder architecture based on a single-chip dedicated LSI with a control MPU. - Yasushi Ooi; Osamu Ohnishi; Yutaka Yokoyama; Yoichi Katayama; Masayuki Mizuno; Masakazu Yamashina; Hideo Takano; Naoya Hayashi; Ichiro Tamitani (ICASSP, 1997)

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. - Masayuki Mizuno; Yasushi Ooi; Naoya Hayashi; Junichi Goto; Masatoshi Hozumi; Koichiro Furuta; Atsufumi Shibayama; Yoetsu Nakazawa; Osamu Ohnishi; Shu-Yu Zhu; Yutaka Yokoyama; Yoichi Katayama; et al. (IEEE J. Solid State Circuits, 1997)

A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. - Kazumasa Suzuki; Masayuki Daito; Tomoo Inoue; Kouhei Nadehara; Masahiro Nomura; Masayuki Mizuno; Tomofumi Iima; Shoichiro Sato; Terumi Fukuda; Tomohisa Arai; Ichiro Kuroda; Masakazu Yamashina (IEEE J. Solid State Circuits, 1999)

A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. - Koichiro Minami; Muneo Fukaishi; Masayuki Mizuno; Hideaki Onishi; Kenji Noda; Kiyotaka Imai; Tadahiko Horiuchi; Hiroshi Yamaguchi; Takanori Sato; Kazuyuki Nakamura; Masakazu Yaniashina (CICC, 2001)

A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. - Yoshiharu Kudoh; Muneo Fukaishi; Masayuki Mizuno (IEEE J. Solid State Circuits, 2003)

Frequency-hopping vernier clock generators for multiple clock domain SoCs. - Hiroshi Kodama; Masayuki Mizuno; Koichi Nose; Akio Tanaka (CICC, 2004)

A nonvolatile programmable solid-electrolyte nanometer switch. - Shunichi Kaeriyama; Toshitsugu Sakamoto; Hiroshi Sunamura; Masayuki Mizuno; Hisao Kawaura; Tsuyoshi Hasegawa; Kazuya Terabe; Tomonobu Nakayama; Masakazu Aono (IEEE J. Solid State Circuits, 2005)

A 6.7-fF/μm2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL. - Makoto Takamiya; Masayuki Mizuno (IEEE J. Solid State Circuits, 2005)

A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. - Koichi Nose; Mikihiro Kajita; Masayuki Mizuno (ISSCC, 2006)

Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. - Keishi Ohashi; Junichi Fujikata; Masafumi Nakada; Tsutomu Ishi; Kenichi Nishi; Hirohito Yamada; Muneo Fukaishi; Masayuki Mizuno; Koichi Nose; Ichiro Ogura; Yutaka Urino; Toshio Baba (ISSCC, 2006)

Solid-Electrolyte Nanometer Switch. - Naoki Banno; Toshitsugu Sakamoto; Noriyuki Iguchi; Hisao Kawaura; Shunichi Kaeriyama; Masayuki Mizuno; Kazuya Terabe; Tsuyoshi Hasegawa; Masakazu Aono (IEICE Trans. Electron., 2006)

A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. - Koichi Nose; Mikihiro Kajita; Masayuki Mizuno (IEEE J. Solid State Circuits, 2006)

LAGS System Using Data/Instruction Grain Power Control. - Makoto Ikeda; Taku Sogabe; Ken Ishii; Masayuki Mizuno; Toru Nakura; Koichi Nose; Kunihiro Asada (ISSCC, 2007)

A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. - Shunichi Kaeriyama; Mikihiro Kajita; Masayuki Mizuno (ISSCC, 2007)

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. - Toru Nakura; Koichi Nose; Masayuki Mizuno (ISSCC, 2007)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. - Kiichi Niitsu; Noriyuki Miura; Mari Inoue; Yoshihiro Nakagawa; Masamoto Tago; Masayuki Mizuno; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

LSI On-Chip Optical Interconnection with Si Nano-Photonics. - Junichi Fujikata; Kenichi Nishi; Akiko Gomyo; Jun Ushida; Tsutomu Ishi; Hiroaki Yukawa; Daisuke Okamoto; Masafumi Nakada; Takanori Shimizu; Masao Kinoshita; Koichi Nose; Masayuki Mizuno; et al. (IEICE Trans. Electron., 2008)

A 0.016 mm2, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis. - Koichi Nose; Masayuki Mizuno (IEEE J. Solid State Circuits, 2008)

Basis-motion torque composition approach: generation of feedforward inputs for control of multi-joint robots. - Masahiro Sekimoto; Sadao Kawamura; Tomoya Ishitsubo; Shinsuke Akizuki; Masayuki Mizuno (IROS, 2009)

A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery. - Koichi Yamaguchi; Yoshihiko Hori; Keiichi Nakajima; Kazumasa Suzuki; Masayuki Mizuno; Hiroshi Hayama (ISSCC, 2009)

Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Tadahiro Kuroda; Masayuki Mizuno (ISSCC, 2009)

Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits. - Katsu Nakamura; Masayuki Mizuno (IEEE J. Solid State Circuits, 2009)

A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery. - Koichi Yamaguchi; Yoshihiko Hori; Keiichi Nakajima; Kazumasa Suzuki; Masayuki Mizuno; Hiroshi Hayama (IEEE J. Solid State Circuits, 2009)

On-Chip Optical Interconnect. - Keishi Ohashi; Kenichi Nishi; Takanori Shimizu; Masafumi Nakada; Junichi Fujikata; Jun Ushida; Sunao Torii; Koichi Nose; Masayuki Mizuno; Hiroaki Yukawa; Masao Kinoshita; Nobuo Suzuki; et al. (Proc. IEEE, 2009)

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. - Tsutomu Takeya; Kazuhisa Sunaga; Koichi Yamaguchi; Hideyuki Sugita; Yoichi Yoshida; Masayuki Mizuno; Tadahiro Kuroda (CICC, 2010)

A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. - Eisuke Saneyoshi; Koichi Nose; Masayuki Mizuno (ISSCC, 2010)

A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. - Hideyuki Sugita; Kazuhisa Sunaga; Koichi Yamaguchi; Masayuki Mizuno (ISSCC, 2010)

Gate-oxide early-life failure identification using delay shifts. - Young Moon Kim; Tze Wee Chen; Yoshio Kameda; Masayuki Mizuno; Subhasish Mitra (VTS, 2010)

A 0.2 mm 2 , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability. - Haruya Ishizaki; Masayuki Mizuno (IEEE J. Solid State Circuits, 2010)

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. - Hideaki Saito; Masayuki Nakajima; Takumi Okamoto; Yusuke Yamada; Akira Ohuchi; Noriyuki Iguchi; Toshitsugu Sakamoto; Koichi Yamaguchi; Masayuki Mizuno (IEEE J. Solid State Circuits, 2010)

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. - Yoichi Yoshida; Koichi Nose; Yoshihiro Nakagawa; Koichiro Noguchi; Yasuhiro Morita; Masamoto Tago; Masayuki Mizuno; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. - Shunichi Kaeriyama; Mikihiro Kajita; Masayuki Mizuno (IEICE Trans. Electron., 2011)

Dicode Partial Response Signaling over Inductively-Coupled Channel. - Koichi Yamaguchi; Masayuki Mizuno (IEICE Trans. Electron., 2011)

A Duobinary Signaling for Asymmetric Multi-Chip Communication. - Koichi Yamaguchi; Masayuki Mizuno (IEICE Trans. Electron., 2011)

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. - Takashi Tokairin; Koichi Nose; Koichi Takeda 001; Koichiro Noguchi; Tadashi Maeda; Kazuyoshi Kawai; Masayuki Mizuno (VLSIC, 2012)

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. - Yoshifumi Ikenaga; Masahiro Nomura; Shuji Suenaga; Hideo Sonohara; Yoshitaka Horikoshi; Toshiyuki Saito; Yukio Ohdaira; Yoichiro Nishio; Tomohiro Iwashita; Miyuki Satou; Koji Nishida; Koichi Nose; et al. (IEEE J. Solid State Circuits, 2012)

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. - Shunichi Kaeriyama; Shinichi Uchida; Masayuki Furumiya; Mitsuji Okada; Tadashi Maeda; Masayuki Mizuno (IEEE J. Solid State Circuits, 2012)

A 5.5Gb/s 5mm contactless interface containing a 50Mb/s bidirectional sub-channel employing common-mode OOK signaling. - Ken'ichiro Hijioka; Masaharu Matsudaira; Koichi Yamaguchi; Masayuki Mizuno (ISSCC, 2013)

Formal Verification of the Correspondence Between Call-by-Need and Call-by-Name. - Masayuki Mizuno; Eijiro Sumii (FLOPS, 2018)

Formal Verifications of Call-by-Need and Call-by-Name Evaluations with Mutual Recursion. - Masayuki Mizuno; Eijiro Sumii (APLAS, 2019)

The numerical analysis of mass evacuation in Taipei 101 with control volume model. - Guan-Yuan Wu; Masayuki Mizuno (Simul. Model. Pract. Theory, 2019)