A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates. - Nobuo Tamba; Akio Anzai; Kazuhiro Akimoto; Masayuki Ohayashi; Toshiro Hiramoto; Tadanori Kokubu; Sohei Ohmori; Tetsuya Muraya; Atsuyuki Kishimoto; Sousuke Tsuji; Hideki Hayashi; Nadateru Handa; et al. (IEEE J. Solid State Circuits, 1994)

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. - Hiroalu Nambu; Kazuo Kanetani; Youji Idei; Tom Masuda; Keiichi Higeta; Masayuki Ohayashi; Masami Usami; Kunihiko Yamaguchi; Toshiyuki Kikuchi; Takahide Ikeda; Kenichi Ohhata; Takeshi Kusunoki; et al. (IEEE J. Solid State Circuits, 1995)

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. - Keiichi Higeta; Masami Usami; Masayuki Ohayashi; Yasuhiro Fujimura; Masahiko Nishiyama; Satoru Isomura; Kunihiko Yamaguchi; Youji Idei; Hiroaki Nambu; Kenichi Ohhata; Nadateru Hanta (IEEE J. Solid State Circuits, 1996)