A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. - Hiroyuki Nakahara; Haruyoshi Yonekawa; Tomoya Fujii; Masayuki Shimoda; Simpei Sato (FPL, 2017)

All binarized convolutional neural network and its implementation on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (FPT, 2017)

A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2). - Hiroki Nakahara; Masayuki Shimoda; Shimpei Sato (FPL, 2018)

Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (FPL, 2018)

A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector. - Hiroki Nakahara; Masayuki Shimoda; Shimpei Sato (FPT, 2018)

Power Efficient Object Detector with an Event-Driven Camera on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (HEART, 2018)

Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. - Masayuki Shimoda; Youki Sada; Hiroki Nakahara (ARC, 2019)

An FPGA-based Fine Tuning Accelerator for a Sparse CNN. - Hiroki Nakahara; Akira Jinguji; Masayuki Shimoda; Shimpei Sato (FPGA, 2019)

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network. - Hiroki Nakahara; Youki Sada; Masayuki Shimoda; Kouki Sayama; Akira Jinguji; Shimpei Sato (FPL, 2019)

An FPGA Implementation of Real-Time Object Detection with a Thermal Camera. - Masayuki Shimoda; Youki Sada; Ryosuke Kuramochi; Hiroki Nakahara (FPL, 2019)

A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. - Youki Sada; Masayuki Shimoda; Akira Jinguji; Hiroki Nakahara (FPT, 2019)

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks. - Ryosuke Kuramochi; Youki Sada; Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (MCSoC, 2019)

FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System. - Ryosuke Kuramochi; Masayuki Shimoda; Youki Sada; Shimpei Sato; Hiroki Nakahara (ReConFig, 2019)

GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers. - Hiroki Nakahara; Haruyoshi Yonekawa; Tomoya Fujii; Masayuki Shimoda; Shimpei Sato (IEICE Trans. Inf. Syst., 2019)

Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA. - Masayuki Shimoda; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2019)

Fast Monocular Depth Estimation on an FPGA. - Youki Sada; Naoto Soga; Masayuki Shimoda; Akira Jinguji; Shimpei Sato; Hiroki Nakahara (IPDPS Workshops, 2020)

SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators. - Masayuki Shimoda; Youki Sada; Ryosuke Kuramochi; Shimpei Sato; Hiroki Nakahara (IEICE Trans. Inf. Syst., 2020)

Mask RSA: End-To-End Reinforcement Learning-based Routing and Spectrum Assignment in Elastic Optical Networks. - Masayuki Shimoda; Takafumi Tanaka (ECOC, 2021)

Impact of Operational Mode Selection and Grooming Policies on Auxiliary Graph-Based Multi-layer Network Planning. - Takafumi Tanaka; Masayuki Shimoda (ECOC, 2021)

FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling. - Masayuki Shimoda; Youki Sada; Hiroki Nakahara (J. Signal Process. Syst., 2021)

Pre- and post-processing techniques for reinforcement-learning-based routing and spectrum assignment in elastic optical networks. - Takafumi Tanaka; Masayuki Shimoda (J. Opt. Commun. Netw., 2023)

A Table Look-Up Based Quantum Simulation Accelerator on an FPGA. - Haruhiko Hasegawa; Masayuki Shimoda; Hiroki Nakahara; Takefumi Miyoshi (ICFPT, 2024)

BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. - Zezhong Wang; Masayuki Shimoda; Atsushi Takahashi 001 (ISCAS, 2024)

Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing. - Masayuki Shimoda; Atsushi Takahashi 001 (ISOCC, 2024)

Gap Channel Routing with Fixed Wires. - Masayuki Shimoda; Atsushi Takahashi 001; Kosuke Yanagidaira; Mikiko Hirai; Toshikazu Watanabe; Toshimitsu Iwasawa; Chikaaki Kodama (ISCAS, 2025)

A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. - Haruhiko Hasegawa; Masayuki Shimoda; Hiroki Nakahara; Takefumi Miyoshi (ISMVL, 2025)

Gridless Gap Channel Routing with Variable-Width Wires. - Masayuki Shimoda; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

UEO Channel Routing Algorithm to Alleviate Local Congestion for Generalized Channels. - Zezhong Wang; Hiroto Nakayama; Masayuki Shimoda; Atsushi Takahashi 001; Kosuke Yanagidaira; Chikaaki Kodama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

SDG Channel Routing to Minimize Wirelength for Generalized Channel. - Zezhong Wang; Masayuki Shimoda; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Gridless Gap Channel Routing to Minimize Wirelength. - Masayuki Shimoda; Atsushi Takahashi 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2025)