Resilient Cell-Based Architecture for Time-to-Digital Converter. - Chia-Hua Wu; Shi-Yu Huang; Mason Chern; Yung-Fa Chou; Ding-Ming Kwai (ISVLSI, 2017)

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Hans Tsai; Wu-Tung Cheng (ASP-DAC, 2019)

Layout-Based Dual-Cell-Aware Tests. - Tse-Wei Wu; Dong-Zhen Lee; Yu-Hao Huang; Mango C.-T. Chao; Kai-Chiang Wu; Shu-Yi Kao; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee (VTS, 2019)

CNN-based Stochastic Regression for IDDQ Outlier Identification. - Chun-Teng Chen; Chia-Heng Yen; Cheng-Yen Wen; Cheng-Hao Yang; Kai-Chiang Wu; Mason Chern; Ying-Yen Chen; Chun-Yi Kuo; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (VTS, 2020)

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. - Cheng-Hao Yang; Chia-Heng Yen; Ting-Rui Wang; Chun-Teng Chen; Mason Chern; Ying-Yen Chen; Jih-Nung Lee; Shu-Yi Kao; Kai-Chiang Wu; Mango Chia-Tso Chao (VTS, 2021)

Diagnosing Double Faulty Chains through Failing Bit Separation. - Cheng-Sian Kuo; Bing-Han Hsieh; James Chien-Mo Li; Chris Nigh; Gaurav Bhargava; Mason Chern (ITC, 2022)

Methodology of Generating Timing-Slack-Based Cell-Aware Tests. - Yu-Teng Nien; Kai-Chiang Wu; Dong-Zhen Lee; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. - Bing-Han Hsieh; Yun-Sheng Liu; James Chien-Mo Li; Chris Nigh; Mason Chern; Gaurav Bhargava (ITC, 2023)