Power and delay optimization for network on chip. - Mohsen Nickray; Masoud Dehyadegari; Ali Afzali-Kusha (ECCTD, 2005)

A New Protocol Stack Model for Network on Chip. - Masood Deh-Yadegari; Mohsen Nickray; Ali Afzali-Kusha; Zainalabedin Navabi (ISVLSI, 2006)

Emotion on FPGA: Model driven approach. - Mohammad Reza Jamali; Arash Arami; Masood Deh-Yadegari; Caro Lucas; Zainalabedin Navabi (Expert Syst. Appl., 2009)

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization. - Mehdi Kamal; Neda Kazemian Amiri; Arezoo Kamran; Seyyed Alireza Hoseini; Masoud Dehyadegari; Hamid Noori (ASAP, 2010)

Real-time embedded emotional controller. - Mohammad Reza Jamali; Masood Deh-Yadegari; Arash Arami; Caro Lucas; Zainalabedin Navabi (Neural Comput. Appl., 2010)

An adaptive fuzzy logic-based routing algorithm for networks-on-chip. - Masoud Dehyadegari; Masoud Daneshtalab; Masoumeh Ebrahimi; Juha Plosila; Siamak Mohammadi (AHS, 2011)

A tightly-coupled multi-core cluster with shared-memory HW accelerators. - Masoud Dehyadegari; Andrea Marongiu; Mohammad Reza Kakoee; Luca Benini; Siamak Mohammadi; Nasser Yazdani (ICSAMOS, 2012)

Distributed fair DRAM scheduling in network-on-chips architecture. - Masoud Dehyadegari; Siamak Mohammadi; Nasser Yazdani (J. Syst. Archit., 2013)

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip. - Masoumeh Ebrahimi; Hannu Tenhunen; Masoud Dehyadegari (J. Syst. Archit., 2013)

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators. - Masoud Dehyadegari; Andrea Marongiu; Mohammad Reza Kakoee; Siamak Mohammadi; Nasser Yazdani; Luca Benini (IEEE Trans. Computers, 2015)

Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks. - Sarvenaz Tajasob; Morteza Rezaalipour; Masoud Dehyadegari; Mahdi Nazm Bojnordi (ISLPED, 2018)

Enhanced graph processing in PIM accelerators with improved queue management. - Mohammad Amin Mosayebi; Arghavan Mohammadhassani; Masoud Dehyadegari (Microelectron. J., 2019)

IDrAx: A tool-chain for designing efficient approximate adders. - Morteza Rezaalipour; Mohammad Rezaalipour; Sarvenaz Tajasob; Masoud Dehyadegari (Microelectron. J., 2019)

Designing energy-efficient imprecise adders with multi-bit approximation. - Sarvenaz Tajasob; Morteza Rezaalipour; Masoud Dehyadegari (Microelectron. J., 2019)

AxMAP: Making Approximate Adders Aware of Input Patterns. - Morteza Rezaalipour; Mohammad Rezaalipour; Masoud Dehyadegari; Mahdi Nazm Bojnordi (IEEE Trans. Computers, 2020)

Memristive Data Ranking. - Ananth Krishna Prasad; Morteza Rezaalipour; Masoud Dehyadegari; Mahdi Nazm Bojnordi (HPCA, 2021)

G-Arrays: Geometric Arrays for Efficient Point Cloud Processing. - Hoda Roodaki; Masoud Dehyadegari; Mahdi Nazm Bojnordi (ICASSP, 2021)

Linear-time error calculation for approximate adders. - Morteza Rezaalipour; Masoud Dehyadegari (Comput. Electr. Eng., 2021)

Accurate Low-Bit Length Floating-Point Arithmetic with Sorting Numbers. - Alireza Dehghanpour; Javad Khodamoradi Kordestani; Masoud Dehyadegari (Neural Process. Lett., 2023)

Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems. - Morteza Amouzegar; Morteza Rezaalipour; Masoud Dehyadegari (ACM J. Emerg. Technol. Comput. Syst., 2024)

A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding. - Sina Shah Oveisi; Hoda Roodaki; Morteza Rezaalipour; Masoud Dehyadegari (Multim. Tools Appl., 2024)

Point cloud downsampling based on the transformer features. - Alireza Dehghanpour; Zahra Sharifi; Masoud Dehyadegari (Vis. Comput., 2025)