A 16-channel 1.1mm2 implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS. - Mahsa Shoaran; Masoud Shahshahani; Masoud Farivar; Joyel Almajano; Amirhossein Shahshahani; Alexandre Schmid; Anatol Bragin; Yusuf Leblebici; Azita Emami (VLSI Circuits, 2016)

MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (FPGA, 2020)

Resource and Performance Estimation for CNN Models using Machine Learning. - Masoud Shahshahani; Dinesh Bhatia (ISVLSI, 2021)

An Automated Tool for Implementing Deep Neural Networks on FPGA. - Masoud Shahshahani; Mohammad Sabri Abrebekoh; Bahareh Khabbazan; Dinesh Bhatia (VLSID, 2021)

MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (LASCAS, 2022)

PPA Based CNN Architecture Explorer. - Masoud Shahshahani; Dinesh Bhatia (LASCAS, 2022)

Robust Estimation of FPGA Resources and Performance from CNN Models. - Pingakshya Goswami; Masoud Shahshahani; Dinesh Bhatia (VLSID, 2022)

A 74W/48V Monolithic-GaN Integrated Adjustable Multilevel Supply Modulator for 5G Base-Station Massive-MIMO Arrays. - Hieu Minh Pham; Peter M. Asbeck; Donald F. Kimball; Navneet Sharma; Shenggang Dong; Masoud Shahshahani; Won-Suk Choi 004; Gary Xu; Marcus Michel; Ratul Das; Robert Beach; Hanh-Phuc Le (ISSCC, 2025)