A high-speed low-voltage phase detector for clock recovery from NRZ data. - Francesco Centurelli; Massimo Pozzoni; Giuseppe Scotti; Alessandro Trifiletti (ISCAS (4), 2004)

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability. - Francesco Centurelli; Alessandro Golfarelli; Jesus Guinea; Leonardo Masini; Damiana Morigi; Massimo Pozzoni; Giuseppe Scotti; Alessandro Trifiletti (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR. - Simone Erba; Massimo Pozzoni; Matteo Pisati; Riccardo Brama; Davide Sanzogni; Emanuele Depaoli; Paolo Viola; Francesco Svelto (CICC, 2008)

A sliding IF receiver for mm-wave WLANs in 65nm CMOS. - Stefano Bozzola; Davide Guermandi; Federico Vecchi; Matteo Repossi; Massimo Pozzoni; Andrea Mazzanti; Francesco Svelto (CICC, 2009)

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. - Massimo Pozzoni; Simone Erba; Paolo Viola; Matteo Pisati; Emanuele Depaoli; Davide Sanzogni; Riccardo Brama; Daniele Baldi; Matteo Repossi; Francesco Svelto (IEEE J. Solid State Circuits, 2009)

A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS. - Andrea Mazzanti; Enrico Monaco; Massimo Pozzoni; Francesco Svelto (ISSCC, 2010)

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. - Massimo Pozzoni; Simone Erba; Davide Sanzogni; Marcello Ganzerli; Paolo Viola; Daniele Baldi; Matteo Repossi; Giorgio Spelgatti; Francesco Svelto (ISSCC, 2010)

A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators. - Federico Vecchi; Stefano Bozzola; Massimo Pozzoni; Davide Guermandi; Enrico Temporiti; Matteo Repossi; Ugo Decanis; Andrea Mazzanti; Francesco Svelto (ISSCC, 2010)

Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications. - Enrico Monaco; Massimo Pozzoni; Francesco Svelto; Andrea Mazzanti (IEEE J. Solid State Circuits, 2010)

A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS. - Federico Vecchi; Stefano Bozzola; Enrico Temporiti; Davide Guermandi; Massimo Pozzoni; Matteo Repossi; Marco Cusmai; Ugo Decanis; Andrea Mazzanti; Francesco Svelto (IEEE J. Solid State Circuits, 2011)

A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS. - Francesco Radice; Melchiorre Bruccoleri; Marcello Ganzerli; Giorgio Spelgatti; Davide Sanzogni; Massimo Pozzoni; Andrea Mazzanti (ESSCIRC, 2013)

A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. - Emanuele Depaoli; Enrico Monaco; Giovanni Steffan; Marco Mazzini; Hongyang Zhang; Walter Audoglio; Oscar Belotti; Augusto Andrea Rossi; Guido Albasini; Massimo Pozzoni; Simone Erba; Andrea Mazzanti (ISSCC, 2018)

A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS. - Emanuele Depaoli; Hongyang Zhang; Marco Mazzini; Walter Audoglio; Augusto Andrea Rossi; Guido Albasini; Massimo Pozzoni; Simone Erba; Enrico Temporiti; Andrea Mazzanti (IEEE J. Solid State Circuits, 2019)