Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. - Carmelo Felicetti; Angelo Furfaro; Domenico Saccà; Massimo Vatalaro; Marco Lanuzza; Felice Crupi (IDCS, 2019)

Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. - Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi (ICECS 2022, 2022)

Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. - Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi (IEEE J. Solid State Circuits, 2022)

Experimental analysis of variability in WS2-based devices for hardware security. - Massimo Vatalaro; H. Neill; F. Gity; Paolo Magnone; Vincenzo Maccaronio; C. Márquez; J. C. Galdon; F. Gamiz; Felice Crupi; P. Hurley; Raffaele De Rose (CoRR, 2023)

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. - Fanny Spagnolo; Stefania Perri; Massimo Vatalaro; Fabio Frustaci; Felice Crupi; Pasquale Corsonello (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Design of a Temperature-Aware Voltage Generator for 2-Bit Read Operation in STT-MRAM Based SIMPLY Architecture. - Massimo Vatalaro; Vincenzo Maccaronio; Tommaso Zanotti; Erika Borellini; Felice Crupi; Francesco Maria Puglisi; Raffaele De Rose (ICICDT, 2025)

Design for Reliability of Multi-Bit Operations in RRAM-Based SIMPLY Logic-in-Memory Circuits. - Tommaso Zanotti; Erika Borellini; Massimo Vatalaro; Vincenzo Maccaronio; Paolo Pavan; Raffaele De Rose; Francesco Maria Puglisi (ICICDT, 2025)

A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider. - Massimo Vatalaro; Raffaele De Rose; Vincenzo Maccaronio; Marco Lanuzza; Felice Crupi (ISCAS, 2025)

PUF-Based Authentication-Oriented Architecture for Identification Tags. - Antonino Rullo; Carmelo Felicetti; Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Domenico Saccà (IEEE Trans. Dependable Secur. Comput., 2025)

C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs. - Fanny Spagnolo; Massimo Vatalaro; Stefania Perri; Felice Crupi; Pasquale Corsonello (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations. - Massimo Vatalaro; Raffaele De Rose; Vincenzo Maccaronio; Marco Lanuzza; Felice Crupi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)