Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. - Fulvio Corno; Paolo Prinetto; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Asian Test Symposium, 1997)

Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. - Fulvio Corno; Paolo Prinetto; Matteo Sonza Reorda; Massimo Violante (DATE, 1998)

Optimal Vector Selection for Low Power BIST. - Fulvio Corno; Matteo Sonza Reorda; Maurizio Rebaudengo; Massimo Violante (DFT, 1999)

Soft-Error Detection through Software Fault-Tolerance Techniques. - Maurizio Rebaudengo; Matteo Sonza Reorda; Marco Torchiano; Massimo Violante (DFT, 1999)

A new BIST architecture for low power circuits. - Fulvio Corno; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (ETW, 1999)

Test Pattern Generation Under Low Power Constraints. - Fulvio Corno; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (EvoWorkshops, 1999)

ALPS: A Peak Power Estimation Tool for Sequential Circuits. - Fulvio Corno; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Great Lakes Symposium on VLSI, 1999)

SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. - Fulvio Corno; Uwe Gläser; Paolo Prinetto; Matteo Sonza Reorda; Heinrich Theodor Vierhaus; Massimo Violante (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Automatic test bench generation for simulation-based validation. - Marcello Lajolo; Luciano Lavagno; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (CODES, 2000)

Evaluating System Dependability in a Co-Design Framework. - Marcello Lajolo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Luciano Lavagno (DATE, 2000)

An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. - Maurizio Rebaudengo; Matteo Sonza Reorda; Marco Torchiano; Massimo Violante (DFT, 2000)

CA-CSTP: a new BIST architecture for sequential circuits. - Fulvio Corno; Matteo Sonza Reorda; Giovanni Squillero; Massimo Violante (ETW, 2000)

System-level test bench generation in a co-design framework. - Marcello Lajolo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Luciano Lavagno (ETW, 2000)

Prediction of Power Requirements for High-Speed Circuits. - Fulvio Corno; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (EvoWorkshops, 2000)

Behavioral-level test vector generation for system-on-chip designs. - Marcello Lajolo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Luciano Lavagno (HLDVT, 2000)

A genetic algorithm-based system for generating test programs for microprocessor IP cores. - Fulvio Corno; Matteo Sonza Reorda; Giovanni Squillero; Massimo Violante (ICTAI, 2000)

New Techniques for Accelerating Fault Injection in VHDL Descriptions. - B. Parrotta; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (IOLTW, 2000)

Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Ph. Cheynet; Bogdan Nicolescu; Raoul Velazco (IOLTW, 2000)

Hardening the Software with Respect to Transient Errors: a Method and Experimental Results. - Ph. Cheynet; Raoul Velazco; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (LATW, 2000)

Early Power Estimation for System-on-Chip Designs. - Marcello Lajolo; Luciano Lavagno; Matteo Sonza Reorda; Massimo Violante (PATMOS, 2000)

Speeding-Up Fault Injection Campaigns in VHDL Models. - B. Parrotta; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (SAFECOMP, 2000)

Low Power BIST via Non-Linear Hybrid Cellular Automata. - Fulvio Corno; Maurizio Rebaudengo; Matteo Sonza Reorda; Giovanni Squillero; Massimo Violante (VTS, 2000)

FPGA-Based Fault Injection for Microprocessor Systems. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Asian Test Symposium, 2001)

System safety through automatic high-level code transformations: an experimental evaluation. - Ph. Cheynet; Bogdan Nicolescu; Raoul Velazco; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DATE, 2001)

On the test of microprocessor IP cores. - Fulvio Corno; Matteo Sonza Reorda; Giovanni Squillero; Massimo Violante (DATE, 2001)

Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DFT, 2001)

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (FPL, 2001)

Exploiting FPGA for Accelerating Fault Injection Experiments. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (IOLTW, 2001)

A Source-to-Source Compiler for Generating Dependable Software. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Marco Torchiano (SCAM, 2001)

Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. - Marcello Lajolo; Matteo Sonza Reorda; Massimo Violante (VLSI Design, 2001)

A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. - Pierluigi Civera; Luca Macchiarulo; Massimo Violante (DFT, 2002)

A New Functional Fault Model for FPGA Application-Oriented Testing. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DFT, 2002)

Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments. - Matteo Sonza Reorda; Massimo Violante (DFT, 2002)

Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (FPL, 2002)

High-level and hierarchical test sequence generation. - Gert Jervan; Zebo Peng; Olga Goloubeva; Matteo Sonza Reorda; Massimo Violante (HLDVT, 2002)

A hierarchical approach for designing dependable systems. - Matteo Sonza Reorda; Massimo Violante; Nicola Mazzocca; Salvatore Venticinque; Andrea Bobbio; Giuliana Franceschinis (HLDVT, 2002)

Analysis of SEU Effects in a Pipelined Processor. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (IOLTW, 2002)

A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks. - Bogdan Nicolescu; Raoul Velazco; Matteo Sonza Reorda; Maurizio Rebaudengo; Massimo Violante (SBCCI, 2002)

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (J. Electron. Test., 2002)

A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. - Paolo Bernardi; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DATE, 2003)

An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DATE, 2003)

Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. - Abdelaziz Ammari; Régis Leveugle; Matteo Sonza Reorda; Massimo Violante (DFT, 2003)

Soft-Error Detection Using Control Flow Assertions. - Olga Goloubeva; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DFT, 2003)

Dependability Analysis of CAN Networks: An Emulation-Based Approach. - Julio Pérez; Matteo Sonza Reorda; Massimo Violante (DFT, 2003)

Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits. - Matteo Sonza Reorda; Massimo Violante (FPL, 2003)

High-level test generation for hardware testing and software validation. - Olga Goloubeva; Matteo Sonza Reorda; Massimo Violante (HLDVT, 2003)

An RT-level Concurrent Error Detection Technique for Data Dominated Systems. - Olga Goloubeva; Matteo Sonza Reorda; Massimo Violante (IOLTS, 2003)

Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. - Matteo Sonza Reorda; Massimo Violante (IOLTS, 2003)

Analyzing SEU Effects in SRAM-based FPGAs. - Massimo Violante; M. Ceschia; Matteo Sonza Reorda; Alessandro Paccagnella; Paolo Bernardi; Maurizio Rebaudengo; D. Bortolato; M. Bellato; P. Zambolin; A. Candelori (IOLTS, 2003)

Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. - Davide Appello; Paolo Bernardi; Alessandra Fudoli; Maurizio Rebaudengo; Matteo Sonza Reorda; Vincenzo Tancorre; Massimo Violante (ITC, 2003)

Accurate Dependability Analysis of CAN-Based Networked Systems. - Julio Pérez; Matteo Sonza Reorda; Massimo Violante (SBCCI, 2003)

Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (J. Electron. Test., 2003)

New techniques for efficiently assessing reliability of SOCs. - Pierluigi Civera; Luca Macchiarulo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Microelectron. J., 2003)

A local analysis of the genotype-fitness mapping in hardware optimization problems. - Ernesto Sánchez 001; Giovanni Squillero; Massimo Violante (IEEE Congress on Evolutionary Computation, 2004)

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. - M. Bellato; Paolo Bernardi; D. Bortolato; A. Candelori; M. Ceschia; Alessandro Paccagnella; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; P. Zambolin (DATE, 2004)

Automatic Generation of Validation Stimuli for Application-Specific Processors. - Olga Goloubeva; Matteo Sonza Reorda; Massimo Violante (DATE, 2004)

On-Line Analysis and Perturbation of CAN Networks. - Matteo Sonza Reorda; Massimo Violante (DFT, 2004)

Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems. - Ernesto Sánchez 001; Giovanni Squillero; Massimo Violante (EvoWorkshops, 2004)

Validation of the dependability of CAN-based networked systems. - Fulvio Corno; Julio Pérez Acle; Mattia Ramasso; Matteo Sonza Reorda; Massimo Violante (HLDVT, 2004)

On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. - Paolo Bernardi; Matteo Sonza Reorda; Luca Sterpone; Massimo Violante (IOLTS, 2004)

Hybrid Soft Error Detection by Means of Infrastructure IP Cores. - Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Fabian Vargas 001; Massimo Violante (IOLTS, 2004)

A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. - Fulvio Corno; Julio Pérez Acle; Matteo Sonza Reorda; Massimo Violante (SBCCI, 2004)

A New Approach to Software-Implemented Fault Tolerance. - Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (J. Electron. Test., 2004)

A New Approach to the Analysis of Single Event Transients in VLSI Circuits. - Matteo Sonza Reorda; Massimo Violante (J. Electron. Test., 2004)

Efficient analysis of single event transients. - Matteo Sonza Reorda; Massimo Violante (J. Syst. Archit., 2004)

An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. - Paolo Bernardi; Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (DFT, 2005)

A design flow for protecting FPGA-based systems against single event upsets. - Luca Sterpone; Massimo Violante (DFT, 2005)

On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. - Paolo Bernardi; Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Fabian Vargas 001; Massimo Violante (DSN, 2005)

Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. - Matteo Sonza Reorda; Luca Sterpone; Massimo Violante (ETS, 2005)

New evolutionary techniques for test-program generation for complex microprocessor cores. - Ernesto Sánchez 001; Massimiliano Schillaci; Matteo Sonza Reorda; Giovanni Squillero; Luca Sterpone; Massimo Violante (GECCO, 2005)

Efficient Estimation of SEU Effects in SRAM-Based FPGAs. - Matteo Sonza Reorda; Luca Sterpone; Massimo Violante (IOLTS, 2005)

Automatic generation of test sets for SBST of microprocessor IP cores. - Ernesto Sánchez 001; Matteo Sonza Reorda; Giovanni Squillero; Massimo Violante (SBCCI, 2005)

Software-Implemented Hardware Fault Tolerance. - Olga Goloubeva; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (Springer, 2006)

A new approach to compress the configuration information of programmable devices. - Maurizio Martina; Guido Masera; Andrea Molino; Fabrizio Vacca; Luca Sterpone; Massimo Violante (DATE Designers' Forum, 2006)

ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. - Luca Sterpone; Massimo Violante (DDECS, 2006)

Online hardening of programs against SEUs and SETs. - Carlos Arthur Lang Lisbôa; Luigi Carro; Matteo Sonza Reorda; Massimo Violante (DFT, 2006)

Combined software and hardware techniques for the design of reliable IP processors. - Maurizio Rebaudengo; Luca Sterpone; Massimo Violante; Cristiana Bolchini; Antonio Miele; Donatella Sciuto (DFT, 2006)

Fault Injection-based Reliability Evaluation of SoPCs. - Matteo Sonza Reorda; Luca Sterpone; Massimo Violante; Marta Portela-García; Celia López-Ongil; Luis Entrena (ETS, 2006)

Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. - Matteo Sonza Reorda; Massimo Violante (IOLTS, 2006)

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. - Luca Sterpone; Massimo Violante (IOLTS, 2006)

A Fault Injection Environment for SoPC's Embedded Microprocessors. - Marta Portela-García; Luca Sterpone; Celia López-Ongil; Matteo Sonza Reorda; Massimo Violante (LATW, 2006)

A New Approach to Cope with Single Event Upsets in Processor-based Systems. - Massimiliano Schillaci; Matteo Sonza Reorda; Massimo Violante (LATW, 2006)

Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. - Paolo Bernardi; Letícia Maria Veiras Bolzani; Alberto Manzone; Massimo Osella; Massimo Violante; Matteo Sonza Reorda (MTV, 2006)

Early, Accurate Dependability Analysis of CAN-Based Networked Systems. - Julio Pérez Acle; Matteo Sonza Reorda; Massimo Violante (IEEE Des. Test Comput., 2006)

Hardening FPGA-based Systems Against SEUs: A New Design Methodology. - Luca Sterpone; Massimo Violante (J. Comput., 2006)

A New Hybrid Fault Detection Technique for Systems-on-a-Chip. - Paolo Bernardi; Letícia Maria Veiras Bolzani; Maurizio Rebaudengo; Matteo Sonza Reorda; Fabian Vargas 001; Massimo Violante (IEEE Trans. Computers, 2006)

A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. - Luca Sterpone; Massimo Violante (IEEE Trans. Computers, 2006)

Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs. - Andrea Manuzzato; Paolo Rech; Simone Gerardin; Alessandro Paccagnella; Luca Sterpone; Massimo Violante (DFT, 2007)

Optimization of Self Checking FIR filters by means of Fault Injection Analysis. - Salvatore Pontarelli; Luca Sterpone; Gian Carlo Cardarilli; Marco Re; Matteo Sonza Reorda; Adelio Salsano; Massimo Violante (DFT, 2007)

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. - Luca Sterpone; Massimo Violante (ETS, 2007)

A new decompression system for the configuration process of SRAM-based FPGAS. - Luca Sterpone; Massimo Violante (ACM Great Lakes Symposium on VLSI, 2007)

A new hardware architecture for performing the gridding of DNA microarray images. - Luca Sterpone; Massimo Violante (ACM Great Lakes Symposium on VLSI, 2007)

Validating the dependability of embedded systems through fault injection by means of loadable kernel modules. - Marco Murciano; Massimo Violante (HLDVT, 2007)

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. - Salvatore Pontarelli; Luca Sterpone; Gian Carlo Cardarilli; Marco Re; Matteo Sonza Reorda; Adelio Salsano; Massimo Violante (IOLTS, 2007)

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. - Luca Sterpone; Matteo Sonza Reorda; Massimo Violante; Fernanda Lima Kastensmidt; Luigi Carro (J. Electron. Test., 2007)

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices. - Luca Sterpone; Niccolò Battezzati; Massimo Violante (WREFT@CF, 2008)

Coping with Obsolescence of Processor Cores in Critical Applications. - Francesco Abate; Massimo Violante (DFT, 2008)

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs. - Niccolò Battezzati; Simone Gerardin; Andrea Manuzzato; Alessandro Paccagnella; Sana Rezgui; Luca Sterpone; Massimo Violante (IOLTS, 2008)

Software and Hardware Techniques for SEU Detection in IP Processors. - Cristiana Bolchini; Antonio Miele; Fabio Rebaudengo; Fabio Salice; Donatella Sciuto; Luca Sterpone; Massimo Violante (J. Electron. Test., 2008)

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. - Eduardo Luis Rhod; Carlos Arthur Lang Lisbôa; Luigi Carro; Matteo Sonza Reorda; Massimo Violante (J. Electron. Test., 2008)

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs. - Francesco Abate; Luca Sterpone; Massimo Violante; Fernanda Lima Kastensmidt (DATE, 2009)

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. - Matteo Sonza Reorda; Massimo Violante; Cristina Meinhardt; Ricardo Reis 001 (DATE, 2009)

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. - Matteo Sonza Reorda; Massimo Violante; Cristina Meinhardt; Ricardo Reis 001 (DFT, 2009)

Soft errors in Flash-based FPGAs: Analysis methodologies and first results. - Niccolò Battezzati; Filomena Decuzzi; Luca Sterpone; Massimo Violante (FPL, 2009)

Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. - Niccolò Battezzati; Filomena Decuzzi; Massimo Violante; Michel Briet (IOLTS, 2009)

A low-cost solution for developing reliable Linux-based space computers for on-board data handling. - Massimo Violante; M. L. Esposti (IOLTS, 2009)

Recovery scheme for hardening system on programmable chips. - Cristina Meinhardt; Ricardo Reis 001; Massimo Violante; Matteo Sonza Reorda (LATW, 2009)

An in-vehicle infotainment software architecture based on google android. - Gianpaolo Macario; Marco Torchiano; Massimo Violante (SIES, 2009)

Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications. - Salvatore Campagna; Moazzam Hussain; Massimo Violante (DFT, 2010)

An integrated flow for the design of hardened circuits on SRAM-based FPGAs. - Cristiana Bolchini; Antonio Miele; Chiara Sandionigi; Niccolò Battezzati; Luca Sterpone; Massimo Violante (ETS, 2010)

A new framework for the automatic insertion of mitigation structures in circuits netlists. - Niccolò Battezzati; Davide Serrone; Massimo Violante (IOLTS, 2010)

A framework to support the design of COTS-based reliable space computers for on-board data handling. - Salvatore Campagna; Massimo Violante (IOLTS, 2010)

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs. - Niccolò Battezzati; Luca Sterpone; Massimo Violante; Filomena Decuzzi (VLSI-SoC, 2010)

Boosting software fault injection for dependability analysis of real-time embedded applications. - Gianpiero Cabodi; Marco Murciano; Massimo Violante (ACM Trans. Embed. Comput. Syst., 2010)

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications. - Niccolò Battezzati; Luca Sterpone; Massimo Violante (Springer, 2011)

A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components. - Salvatore Campagna; Moazzam Hussain; Massimo Violante (ARCS Workshops, 2011)

A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. - Enrico Costenaro; Massimo Violante; Dan Alexandrescu (IOLTS, 2011)

Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs. - Hipólito Guzmán-Miranda; Luca Sterpone; Massimo Violante; Miguel A. Aguirre; Manuel Gutiérrez-Rizo (IEEE Trans. Ind. Electron., 2011)

A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. - Massimo Violante; Cristina Meinhardt; Ricardo Reis 001; Matteo Sonza Reorda (IEEE Trans. Ind. Electron., 2011)

An hybrid architecture to detect transient faults in microprocessors: An experimental validation. - Salvatore Campagna; Massimo Violante (DATE, 2012)

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. - Cristiana Bolchini; Antonio Miele; Chiara Sandionigi; Marco Ottavi; Salvatore Pontarelli; Adelio Salsano; Cecilia Metra; Martin Omaña 001; Daniele Rossi 001; Matteo Sonza Reorda; Luca Sterpone; Massimo Violante; et al. (DFT, 2012)

Embedded Low Power Controller for Autonomous Landing of UAV Using Artificial Neural Network. - Ahmad Din; Basilio Bona; Joel Morrissette; Moazzam Hussain; Massimo Violante; M. Fawad Naseem (FIT, 2012)

Preface. - Khaled Benkrid; Didier Keymeulen; David Merodio; Michael Newell; Rainer Wansch; Umeshkumar D. Patel; Ahmet T. Erdogan; Niels Hadaschik; Luca Sterpone; Jelle Poupaert; Massimo Violante (AHS, 2013)

A fully-automated flow for ITAR-free rad-hard Atmel FPGAs. - Nikos Andrikos; Massimo Violante; David Merodio Codinachs (IOLTS, 2013)

Guest Editorial. - Prashant D. Joshi; Massimo Violante (J. Electron. Test., 2013)

Early reliability evaluation of a biomédical system. - Hakob Hakobyan; Paolo Rech; Matteo Sonza Reorda; Massimo Violante (IDT, 2014)

Evaluation of error effects on a biomedical system. - Enea Bagalini; Massimo Violante; H. Hakobyan (EWDTS, 2015)

An Hybrid Architecture for consolidating mixed criticality applications on multicore systems. - Serhiy Avramenko; Stefano Esposito; Massimo Violante; Marco Sozzi; Massimo Traversone; Marco Binello; Marco Terrone (IOLTS, 2015)

Designing Autonomous Race Car Models for Learning Advanced Topics in Hard Real-Time System. - Enea Bagalini; Massimo Violante (Int. J. Robotics Appl. Technol., 2015)

Automotive embedded software architecture in the multi-core age. - Paolo Gai; Massimo Violante (ETS, 2016)

On the robustness of DCT-based compression algorithms for space applications. - Serhiy Avramenko; Matteo Sonza Reorda; Massimo Violante; Görschwin Fey; Jan-Gerd Mess; Robert Schmidt 003 (IOLTS, 2016)

Online time interference detection in mixed-criticality applications on multicore architectures using performance counters. - Stefano Esposito; Massimo Violante; Marco Sozzi; Marco Terrone; Massimo Traversone (IOLTS, 2016)

Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. - Serhiy Avramenko; Matteo Sonza Reorda; Massimo Violante; Görschwin Fey (LATS, 2016)

On the consolidation of mixed criticalities applications on multicore architectures. - Stefano Esposito; Serhiy Avramenko; Massimo Violante (LATS, 2016)

Passengers' Emotions Recognition to Improve Social Acceptance of Autonomous Driving Vehicles. - Jacopo Sini; Antonio Costantino Marceddu; Massimo Violante; Riccardo Dessì (IIH-MSP (1), 2017)

Deterministic network on chip for deploying real time applications on many-core processors. - Stefano Esposito; Massimo Violante (IOLTS, 2017)

Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. - Tino Flenker; Jan Malburg; Görschwin Fey; Serhiy Avramenko; Massimo Violante; Matteo Sonza Reorda (ISVLSI, 2017)

An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard. - Enea Bagalini; Jacopo Sini; Matteo Sonza Reorda; Massimo Violante; H. Klimesch; Peter Sarson (LATS, 2017)

A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. - Serhiy Avramenko; Matteo Sonza Reorda; Massimo Violante; Görschwin Fey (J. Electron. Test., 2017)

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures. - Stefano Esposito; Massimo Violante (J. Electron. Test., 2017)

A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems. - Stefano Esposito; Massimo Violante; Marco Sozzi; Marco Terrone; Massimo Traversone (ACM Trans. Embed. Comput. Syst., 2017)

QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. - Serhiy Avramenko; Siavoosh Payandeh Azad; Stefano Esposito; Behrad Niazmand; Massimo Violante; Jaan Raik; Maksim Jenihhin (DDECS, 2018)

An automatic approach to integration testing for critical automotive software. - Jacopo Sini; A. Mugoni; Massimo Violante; A. Quario; C. Argiri; F. Fusetti (DTIS, 2018)

Computer-Aided Design of Multi-Agent Cyber-Physical Systems. - Jacopo Sini; Massimo Violante; Riccardo Dessì (ETFA, 2018)

Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems. - Stefano Esposito; Serhiy Avramenko; Massimo Violante (IOLTS, 2018)

Real-Time Validation of Fault-Tolerant Mixed-Criticality Systems. - Stefano Esposito; Jacopo Sini; Massimo Violante (IOLTS, 2018)

Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard. - Jacopo Sini; Matteo Sonza Reorda; Massimo Violante; Peter Sarson (IOLTS, 2018)

An Automatic Approach to Perform FMEDA Safety Assessment on Hardware Designs. - Jacopo Sini; Massimo Violante (IOLTS, 2018)

RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC. - Stefano Esposito; Serhiy Avramenko; Massimo Violante (LATS, 2018)

Real-time validation of mixed-criticality applications. - Stefano Esposito; Jacopo Sini; Massimo Violante (LATS, 2018)

Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. - Serhiy Avramenko; Siavoosh Payandeh Azad; Behrad Niazmand; Massimo Violante; Jaan Raik; Maksim Jenihhin (VLSI-SoC, 2018)

Innovative practices on quality levels of A/MS devices. - Wim Dobbelaere; On Semi; Massimo Violante; Turin Polytechnic; Jeff Rearick (VTS, 2018)

A Novel Simulation-Based Approach for ISO 26262 Hazard Analysis and Risk Assessment. - Jacopo Sini; Massimo Violante; V. Dodde; R. Gnaniah; L. Pecorella (IOLTS, 2019)

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems. - Serhiy Avramenko; Massimo Violante (J. Electron. Test., 2019)

Towards Vehicle-Level Simulator Aided Failure Mode, Effect, and Diagnostic Analysis of Automotive Power Electronics Items. - Jacopo Sini; M. D'Auria; Massimo Violante (LATS, 2020)

Effectiveness of Control Flow Checking Algorithms Using a Model-Based Software Design Approach: An Empirical Study. - Mohammadreza Amel Solouki; Jacopo Sini; Massimo Violante (ICECS 2022, 2022)

Use of Facial Expressions to Improve the Social Acceptance of Level 4 and 5 Automated Driving System Equipped Vehicles. - Antonio Costantino Marceddu; Jacopo Sini; Bartolomeo Montrucchio; Massimo Violante (SoftCOM, 2022)

A Novel Algorithm for Detecting the Drowsiness Onset in Real-Time. - Luigi Pugliese; Massimo Violante; Sara Groppo (IEEE Access, 2022)

A Novel Redundant Validation IoT System for Affective Learning Based on Facial Expressions and Biological Signals. - Antonio Costantino Marceddu; Luigi Pugliese; Jacopo Sini; Gustavo Ramirez Espinosa; Mohammadreza Amel Solouki; Pietro Chiavassa; Edoardo Giusto; Bartolomeo Montrucchio; Massimo Violante; Francesco De Pace (Sensors, 2022)

A Simulation-Based Approach to Aid Development of Software-Based Hardware Failure Detection and Mitigation Algorithms of a Mobile Robot System. - Jacopo Sini; Andrea Passarino; Stefano Bonicelli; Massimo Violante (Sensors, 2022)

A New Approach to Selectively Control Flow Checking Methods Compliant with ISO 26262. - Mohammadreza Amel Solouki; Jacopo Sini; Massimo Violante (CF, 2023)

An Embedded Low-Cost Solution for a Fog Computing Device on the Internet of Things. - Pietro d'Agostino; Massimo Violante; Gianpaolo Macario (FMEC, 2023)

A user-extensible solution for deploying fog computing in industrial applications. - Pietro d'Agostino; Massimo Violante; Gianpaolo Macario (ISIE, 2023)

Rule-based Sleep-Apnea detection algorithm. - Luigi Pugliese; Michele Guagnano; Sara Groppo; Massimo Violante; Riccardo Groppo (IWASI, 2023)

Guidelines for Implementing Control Flow Checking into Automotive Embedded Applications Developed with C Language. - Jacopo Sini; Mohammadreza Amel Solouki; Massimo Violante (NorCAS, 2023)

Novel Control Flow Checking Implementations for Automotive Software. - Francesco Cosimi; Jacopo Sini; Antonio Arena; Massimo Violante (SMACD, 2023)

An Experimental Evaluation of Control Flow Checking for Automotive Embedded Applications Compliant With ISO 26262. - Mohammadreza Amel Solouki; Jacopo Sini; Massimo Violante (IEEE Access, 2023)

Towards In-Cabin Monitoring: A Preliminary Study on Sensors Data Collection and Analysis. - Jacopo Sini; Luigi Pugliese; Sara Groppo; Michele Guagnano; Massimo Violante (CoRR, 2023)

Enhancing Automotive Embedded Applications: A Comprehensive Evaluation of Control Flow Checking Methods. - Mohammadreza Amel Solouki; Jacopo Sini; Massimo Violante (DTTIS, 2024)

Optimizing Lstm-Based Temperature Prediction Algorithm for Embedded System Deployment. - Pietro d'Agostino; Massimo Violante; Gianpaolo Macario (ETFA, 2024)

WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU). - Klaus Hofmann; Ferdinand Keil; David Riehl; Alicja Michalowska-Forsyth; Nikolaus Czepl; Sarah Woywod; Dominik Zupan; Mario R. Casu; Carlo Ricciardi; Massimo Violante; Mariagrazia Graziano; Yuri Ardesi; et al. (FIE, 2024)

A Novel Approach to Address Random Hardware Failures for Automotive Application Within the ISO26262 and AUTOSAR Frameworks. - Jacopo Sini; Kiara Scialabba; Massimo Violante; Francesco Cosimi; Antonio Arena (IEEE Access, 2024)

Dependability in Embedded Systems: A Survey of Fault Tolerance Methods and Software-Based Mitigation Techniques. - Mohammadreza Amel Solouki; Shaahin Angizi; Massimo Violante (IEEE Access, 2024)

Improving Software Reliability with Rust: Implementation for Enhanced Control Flow Checking Methods. - Jacopo Sini; Mohammadreza Amel Solouki; Massimo Violante; Giorgio Di Natale (DATE, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)