Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. - Masud H. Chowdhury; Yehea I. Ismail; Chandramouli V. Kashyap; Byron Krauter (ISCAS (4), 2002)

Realizable RLCK circuit crunching. - Chirayu S. Amin; Masud H. Chowdhury; Yehea I. Ismail (DAC, 2003)

Realizable reduction of RLC circuits using node elimination. - Masud H. Chowdhury; Chirayu S. Amin; Yehea I. Ismail; Chandramouli V. Kashyap; Byron Krauter (ISCAS (3), 2003)

Analysis of Coupling Noise in Dynamic Circuit. - Masud H. Chowdhury; Yehea I. Ismail (IWSOC, 2003)

Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]. - Masud H. Chowdhury; Yehea I. Ismail (CICC, 2004)

Possible Noise Failure Modes in Static and Dynamic Circuits. - Masud H. Chowdhury; Yehea I. Ismail (IWSOC, 2004)

Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. - Gokhan Memik; Masud H. Chowdhury; Arindam Mallik; Yehea I. Ismail (DSN, 2005)

Realizable reduction of interconnect circuits including self and mutual inductances. - Chirayu S. Amin; Masud H. Chowdhury; Yehea I. Ismail (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach. - Pervez Khaled; Masud H. Chowdhury (APCCAS, 2006)

Optical Interconnect Technology; Photons Based Signal Communication. - Geetanjali Kshirsagar; Masud H. Chowdhury (APCCAS, 2006)

Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits. - Vivek Nigam; Masud H. Chowdhury; Roland Priemer (APCCAS, 2006)

Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect. - Abinash Roy; Masud H. Chowdhury (APCCAS, 2006)

Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits. - Chuen M. Tan; Masud H. Chowdhury (APCCAS, 2006)

Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining. - Jingye Xu; Masud H. Chowdhury (ICECS, 2006)

Compound noise analysis in digital circuits using blind source separation. - Vivek Nigam; Masud H. Chowdhury; Roland Priemer (ISCAS, 2006)

Realistic scalability of noise in dynamic circuits. - Masud H. Chowdhury; Yehea I. Ismail (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. - Abinash Roy; Noha H. Mahmoud; Masud H. Chowdhury (DAC, 2007)

Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. - Jingye Xu; Abinash Roy; Masud H. Chowdhury (DATE, 2007)

Analysis of Spatial Temperature Distribution in ICs. - Shriram Krishnamoorthy; Masud H. Chowdhury (ICECS, 2007)

Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications. - Md. Sajjad Rahaman; Masud H. Chowdhury (ICECS, 2007)

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects. - Abinash Roy; Sharada Jha; Masud H. Chowdhury (ICECS, 2007)

Accurate Delay Estimation in the Presence of Coupling Noise using Complete Waveform Accuracy. - Jingye Xu; Masud H. Chowdhury (ICECS, 2007)

Global Interconnect Optimization in the Presence of On-chip Inductance. - Abinash Roy; Masud H. Chowdhury (ISCAS, 2007)

Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. - Abinash Roy; Noha H. Mahmoud; Masud H. Chowdhury (ISCAS, 2007)

Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. - Jingye Xu; Abinash Roy; Masud H. Chowdhury (ISCAS, 2007)

Power Consumption and BER of Flip-Flop Inserted Global Interconnect. - Jingye Xu; Abinash Roy; Masud H. Chowdhury (VLSI Design, 2007)

Compact thermal network model: Realization and reduction. - Shriram Krishnamoorthy; Masud H. Chowdhury (EIT, 2008)

BER performance comparison between CDMA and UWB for RF/wireless interconnect application. - Md. Sajjad Rahaman; Masud H. Chowdhury (EIT, 2008)

Improved ber performance in intra-chip rf/wireless interconnect systems. - Md. Sajjad Rahaman; Masud H. Chowdhury (ACM Great Lakes Symposium on VLSI, 2008)

Fast bus waveform estimation at the presence of coupling noise. - Jingye Xu; Pervez Khaled; Masud H. Chowdhury (ACM Great Lakes Symposium on VLSI, 2008)

Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects. - Abinash Roy; Jingye Xu; Masud H. Chowdhury (ICECS, 2008)

Innovative power gating for leakage reduction. - Masud H. Chowdhury; Juliana Gjanci; Pervez Khaled (ISCAS, 2008)

Time diversity approach for intra-chip RF/wireless interconnect systems. - Md. Sajjad Rahaman; Masud H. Chowdhury (ISCAS, 2008)

Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. - Abinash Roy; Masud H. Chowdhury (ISCAS, 2008)

Full waveform accuracy to estimate delay in coupled digital circuits. - Jingye Xu; Pervez Khaled; Masud H. Chowdhury (ISCAS, 2008)

Optimization technique for flip-flop inserted global interconnect. - Jingye Xu; Abinash Roy; Masud H. Chowdhury (ISCAS, 2008)

Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. - Masud H. Chowdhury; Juliana Gjanci; Pervez Khaled (ISVLSI, 2008)

Noise separation in analog integrated circuits using independent component analysis technique. - Jingye Xu; Abinash Roy; Masud H. Chowdhury (Integr. Comput. Aided Eng., 2008)

Compound noise separation in digital circuits using blind source separation. - Jingye Xu; Vivek Nigam; Abinash Roy; Masud H. Chowdhury (Microelectron. J., 2008)

VSIB: A Sensor Bus Architecture for Smart-Sensor Network. - Md. Sajjad Rahaman; Masud H. Chowdhury; Irfan Nasir; Lih-Tyng Hwang (CSIE (3), 2009)

Crosstalk Avoidance and Error-correction Coding for Coupled RLC Interconnects. - Md. Sajjad Rahaman; Masud H. Chowdhury (ISCAS, 2009)

Investigation and a practical compact network model of thermal stress in integrated circuits. - Shriram Krishnamoorthy; Masud H. Chowdhury (Integr. Comput. Aided Eng., 2009)

Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems. - Md. Sajjad Rahaman; Masud H. Chowdhury (Microelectron. J., 2010)

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns. - Abinash Roy; Jingye Xu; Masud H. Chowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Addressing crosstalk issue in on-chip carbon nanotube interconnects using negative capacitance. - Md. Khaled Hassan; Md. Sajjad Rahaman; Masud H. Chowdhury (ISCAS, 2011)

Spatial- and temporal-reliability aware design for nano-scale VLSI circuits. - Md. Sajjad Rahaman; Qing Duan; Masud H. Chowdhury (ISCAS, 2011)

A circuit implementation for dynamic thermal management techniques. - Pritesh Vora; Masud H. Chowdhury (ISCAS, 2011)

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC). - Masud H. Chowdhury; Pervez Khaled; Juliana Gjanci (Circuits Syst. Signal Process., 2011)

A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC). - Juliana Gjanci; Masud H. Chowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Fast Waveform Estimation (FWE) for Timing Analysis. - Jingye Xu; Masud H. Chowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Exploiting negative quantum capacitance of carbon nanotube FETs for low power applications. - Md. Sajjad Rahaman; Masud H. Chowdhury (ISCAS, 2012)

On-chip voltage regulator without physical inductor. - Md. Tanim Humayun; Juliana Gjanci; Masud H. Chowdhury (NEWCAS, 2012)

Thermal aware Graphene based Through Silicon Via design for 3D IC. - Nahid M. Hossain; MunEm Hossain; Abdul Hamid Bin Yousuf; Masud H. Chowdhury (3DIC, 2013)

Active on-chip voltage regulator based on second generation current conveyor. - Emeshaw Ashenafi; Masud H. Chowdhury (ICECS, 2013)

Analytical model to estimate the subthreshold swing of SOI FinFET. - Azzedin D. Es-Sakhi; Masud H. Chowdhury (ICECS, 2013)

Implementation of active floating inductor based on second generation current conveyor for on chip voltage regulator. - Emeshaw Ashenafi; Masud H. Chowdhury (MWSCAS, 2013)

Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design. - Azzedin D. Es-Sakhi; Masud H. Chowdhury (MWSCAS, 2013)

Heat transfer simulations for pulsed laser annealing of silicon thin film. - MunEm Hossain; Masud H. Chowdhury (MWSCAS, 2013)

Analysis of the properties of ZnO nanoparticle for emerging applications in nanoscale domains. - Md Nahid Hossain; Masud H. Chowdhury; Md. Jahidul Islam; Tajmeri Selina Akhter (MWSCAS, 2013)

Multilayer graphene nanoribbon floating gate transistor for flash memory. - Nahid M. Hossain; Masud H. Chowdhury (ISCAS, 2014)

Analysis of RLC interconnect delay model using second order approximation. - Muhammad Sanaullah; Masud H. Chowdhury (ISCAS, 2014)

Transistor doping profile optimization for low power subthreshold circuits. - Munem Hossain; Masud H. Chowdhury (MWSCAS, 2014)

Graphene and CNT based flash memory: Impacts of scaling control and tunnel oxide thickness. - Nahid M. Hossain; Masud H. Chowdhury (MWSCAS, 2014)

A new real pole delay model for RLC interconnect using second order approximation. - Muhammad Sanaullah; Masud H. Chowdhury (MWSCAS, 2014)

Neural network based classification of stressed speech using nonlinear spectral and cepstral features. - Muhammad Sanaullah; Masud H. Chowdhury (NEWCAS, 2014)

Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET). - Azzedin D. Es-Sakhi; Masud H. Chowdhury (SoCC, 2014)

Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET). - Azzedin D. Es-Sakhi; Masud H. Chowdhury (SoCC, 2014)

Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation. - Nahid M. Hossain; Md Belayat Hossain; Masud H. Chowdhury (SoCC, 2014)

A novel memristor emulator based only on an exponential amplifier and CCII+. - Abdullah G. Alharbi; Mohamed E. Fouda; Masud H. Chowdhury (ICECS, 2015)

A new simple emulator circuit for current controlled memristor. - Abdullah G. Alharbi; Zainulabideen J. Khalifa; Mohamed E. Fouda; Masud H. Chowdhury (ICECS, 2015)

Memristor emulator based on single CCII. - Abdullah G. Alharbi; Zainulabideen J. Khalifa; Mohammed E. Fouda; Masud H. Chowdhury (ICM, 2015)

Analysis of subthreshold swing in multichannel tunneling carbon nanotube field effect transistor (MT-CNTFET). - Azzedin D. Es-Sakhi; Masud H. Chowdhury (ISCAS, 2015)

Analysis of radiation effect on the threshold voltage of flash memory device. - Nahid M. Hossain; Jitendra Koppu; Masud H. Chowdhury (ISCAS, 2015)

Multilayer molybdenum disulfide (MoS2) based tunnel transistor. - Muhammad Sanaullah; Masud H. Chowdhury (ISCAS, 2015)

Performance analysis of through silicon via (TSV) and through glass via (TGV) for different materials. - Abdul Hamid Bin Yousuf; Nahid M. Hossain; Masud H. Chowdhury (ISCAS, 2015)

Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET). - Azzedin D. Es-Sakhi; Masud H. Chowdhury (ISQED, 2015)

Memristor emulator based on practical current controlled model. - Abdullah G. Alharbi; Mohammed E. Fouda; Masud H. Chowdhury (MWSCAS, 2015)

High-speed graphene based quantum-optical interconnect design. - Ritesh Chowdri; Nahid M. Hossain; Masud H. Chowdhury (MWSCAS, 2015)

Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). - Azzedin D. Es-Sakhi; Masud H. Chowdhury (MWSCAS, 2015)

New three dimensional doping profile for devices in subthreshold circuit. - MunEm Hossain; Masud H. Chowdhury (MWSCAS, 2015)

Analytical analysis of the contact resistance (Rc) of metal-MoS2 interface. - Munem Hossain; Muhammad Sanaullah; Abdul Hamid Bin Yousuf; Azzedin Es-Saki; Masud H. Chowdhury (MWSCAS, 2015)

Subthreshold swing characteristics of multilayer MoS2 tunnel FET. - Muhammad Sanaullah; Masud H. Chowdhury (MWSCAS, 2015)

Optimization of ON current in multilayer Molybdenum Disulfide (MoS2) based tunnel field effect transistor. - Muhammad Sanaullah; Masud H. Chowdhury (MWSCAS, 2015)

Improved Model for Wire-Length Estimation in Stochastic Wiring Distribution. - Mohamed S. Hefeida; Masud H. Chowdhury (CoRR, 2015)

Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory. - Nahid M. Hossain; Masud H. Chowdhury (ACM J. Emerg. Technol. Comput. Syst., 2015)

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing. - Azzedin D. Es-Sakhi; Masud H. Chowdhury (Microelectron. J., 2015)

Detection of biochemical molecules using CM-SOFFET based biosensor. - Emeshaw Ashenafi; Azzedin D. Es-Sakhi; Masud H. Chowdhury (ISCAS, 2016)

Simple generic memristor emulator for voltage-controlled models. - Abdullah G. Alharbi; Mohammed E. Fouda; Zainulabideen J. Khalifa; Masud H. Chowdhury (MWSCAS, 2016)

Innovative device source/drain and channel implantation for MOS transistors in ultra low power subthreshold circuit applications. - MunEm Hossain; Masud H. Chowdhury (NEWCAS, 2016)

Low voltage Flash memory design based on floating gate SOFFET. - Emeshaw Ashenafi; Azzedin D. Es-Sakhi; Masud H. Chowdhury (SoCC, 2016)

Comprehensive doping scheme for MOSFETs in ultra-low-power subthreshold circuits design. - MunEm Hossain; Masud H. Chowdhury (Microelectron. J., 2016)

BPSK modulation based exact BER computation for network intra-chip RF interconnect. - Muhammad Sana Ullah; Abdullah G. Alharbi; Masud H. Chowdhury (ICM, 2017)

Noise voltage analysis of spiral inductor for on-chip buck converter design. - Emeshaw Ashenafi; Masud H. Chowdhury (ISCAS, 2017)

Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits. - Emeshaw Ashenafi; Azzedin D. Es-Sakhi; Masud H. Chowdhury (ISCAS, 2017)

Impacts of different shapes of through-silicon-via core on 3D IC performance. - Abdul Hamid Bin Yousuf; Nahid M. Hossain; Masud H. Chowdhury (ISCAS, 2017)

Multilayer graphene nanoribbon based BioFET sensor design. - Nahid M. Hossain; Emeshaw Ashenafi; Moqbull Hossen; Azzedin D. Es-Sakhi; Masud H. Chowdhury (MWSCAS, 2017)

Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain. - Nahid M. Hossain; Arif Iqbal; Hemanshu Shishupal; Masud H. Chowdhury (MWSCAS, 2017)

Optimization of subthreshold swing for multilayer MoS2 tunnel transistor. - Muhammad Sana Ullah; Masud H. Chowdhury (MWSCAS, 2017)

Error free sense amplifier circuit design for STT-MRAM nonvolatile memory. - Lohith Kumar Vemula; Nahid M. Hossain; Masud H. Chowdhury (MWSCAS, 2017)

Emerging STT-MRAM circuit and architecture co-design in 45nm technology. - Lohith Kumar Vemula; Nahid M. Hossain; Masud H. Chowdhury (MWSCAS, 2017)

Electrical Nonlinearity Emulation Technique for Current-Controlled Memristive Devices. - Abdullah G. Alharbi; Mohammed E. Fouda; Zainulabideen J. Khalifa; Masud H. Chowdhury (IEEE Access, 2017)

Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. - Azzedin D. Es-Sakhi; Masud H. Chowdhury (Microelectron. J., 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles. - Muhammad Sanaullah; Masud H. Chowdhury (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC). - Nahid M. Hossain; Ritesh Kumar Reddy Kuchukulla; Masud H. Chowdhury (ISCAS, 2018)

Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate. - Marouf Khan; Masud H. Chowdhury (ISCAS, 2018)

An Asynchronous Reconfigurable Switched Capacitor Voltage Regulator. - Farid Uddin Ahmed; Masud H. Chowdhury (MWSCAS, 2018)

A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme. - Mahmood Uddin Mohammed; Nahid M. Hossain; Masud H. Chowdhury (MWSCAS, 2018)

Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate. - Mahmood Uddin Mohammed; Rakesh Vijjapuram; Masud H. Chowdhury (MWSCAS, 2018)

Ternary Device using Graphene Memcapacitor for Post Binary Era. - Jill Arvindbhai Patel; Zarin Tasnim Sandhie; Masud H. Chowdhury (MWSCAS, 2018)

Investigation and Optimization of Spiral Inductor Design for On-Chip Buck Converter. - Emeshaw Ashenafi; Abdul Hamid Bin Yousuf; Masud H. Chowdhury (J. Low Power Electron., 2018)

A New Power Gating Circuit Design Approach Using Double-Gate FDSOI. - Emeshaw Ashenafi; Masud H. Chowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain. - Mahmood Uddin Mohammed; Masud H. Chowdhury (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Design of Energy Efficient SRAM Cell Based on Double Gate Schottky-Barrier-Type GNRFET with Minimum Dimer Lines. - Mahmood Uddin Mohammed; Masud H. Chowdhury (ISCAS, 2019)

A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET. - Mahmood Uddin Mohammed; Athiya Nizam; Liaquat Ali; Masud H. Chowdhury (ISCAS, 2019)

An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V. - Farid Uddin Ahmed; Zarin Tasnim Sandhie; Masud H. Chowdhury (ICCD, 2020)

GNRFET based Ternary Logic - Prospects and Potential Implementation. - Zarin Tasnim Sandhie; Farid Uddin Ahmed; Masud H. Chowdhury (LASCAS, 2020)

Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET. - Zarin Tasnim Sandhie; Farid Uddin Ahmed; Masud H. Chowdhury (MWSCAS, 2020)

A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits. - Farid Uddin Ahmed; Zarin Tasnim Sandhie; Liaquat Ali; Masud H. Chowdhury (IEEE Access, 2021)

FinFET based SRAMs in Sub-10nm domain. - Mahmood Uddin Mohammed; Athiya Nizam; Liaquat Ali; Masud H. Chowdhury (Microelectron. J., 2021)

SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM. - Karthikeyan Nagarajan; Farid Uddin Ahmed; Mohammad Nasim Imtiaz Khan; Asmit De; Masud H. Chowdhury; Swaroop Ghosh (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era. - Zarin Tasnim Sandhie; Jill Arvindbhai Patel; Farid Uddin Ahmed; Masud H. Chowdhury (ACM Comput. Surv., 2022)

Design of novel 3T ternary DRAM with single word-line using CNTFET. - Zarin Tasnim Sandhie; Farid Uddin Ahmed; Masud H. Chowdhury (Microelectron. J., 2022)