A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture. - Kannan Krishna; David A. Yokoyama-Martin; Aaron Caffee; Chris Jones; Mat Loikkanen; James Parker; Ross Segelken; Jeff L. Sonntag; John T. Stonick; Steve Titus; Daniel Weinlader; Skye Wolfer (IEEE J. Solid State Circuits, 2005)