Power switch characterization for fine-grained dynamic voltage scaling. - Liang Di; Mateja Putic; John C. Lach; Benton H. Calhoun (ICCD, 2008)

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. - Mateja Putic; Liang Di; Benton H. Calhoun; John C. Lach (ICCD, 2009)

Flexible Circuits and Architectures for Ultralow Power. - Benton H. Calhoun; Joseph F. Ryan 002; Sudhanshu Khanna; Mateja Putic; John C. Lach (Proc. IEEE, 2010)

Balancing Adder for error tolerant applications. - Matthew Weber; Mateja Putic; Hang Zhang 031; John C. Lach; Jiawei Huang 007 (ISCAS, 2013)

Low Power GPGPU Computation with Imprecise Hardware. - Hang Zhang 031; Mateja Putic; John C. Lach (DAC, 2014)

Hierarchical Temporal Memory on the Automata Processor. - Mateja Putic; A. J. Varshneya; Mircea R. Stan (IEEE Micro, 2017)

Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. - Mateja Putic; Swagath Venkataramani; Schuyler Eldridge; Alper Buyuktosunoglu; Pradip Bose; Mircea Stan (DAC, 2018)