Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors. - Tomás Lang; Mateo Valero; Ignacio Alegre (IEEE Trans. Computers, 1982)

A performance evaluation of the multiple bus network for multiprocessor systems. - Mateo Valero; José María Llabería; Jesús Labarta; Emilio Sanvicente; Tomás Lang (SIGMETRICS, 1983)

Reduction of Connections for Multibus Organization. - Tomás Lang; Mateo Valero; Miguel Angel Fiol (IEEE Trans. Computers, 1983)

Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. - José M. Llabería; Mateo Valero; Enrique Herrada Lillo; Jesús Labarta (ISCA, 1985)

Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. - Juan J. Navarro; José M. Llabería; Mateo Valero (ICPP, 1986)

Computing Size-Independent Matrix Problems on Systolic Array Processors. - Juan J. Navarro; José M. Llabería; Mateo Valero (ISCA, 1986)

Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors. - Juan J. Navarro; José M. Llabería; Mateo Valero (Computer, 1987)

A Discrete Optimization Problem in Local Networks and Data Alignment. - Miguel Angel Fiol; J. Luis A. Yebra; Ignacio Alegre; Mateo Valero (IEEE Trans. Computers, 1987)

Systematic Hardware Adaptation of Systolic Algorithms. - Miguel Valero-García; Juan J. Navarro; José M. Llabería; Mateo Valero (ISCA, 1989)

A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem. - Fernando J. Nuñez; Mateo Valero (J. VLSI Signal Process., 1989)

Implementation of systolic algorithms using pipelined functional units. - Miguel Valero-García; Juan J. Navarro; José M. Llabería; Mateo Valero (ASAP, 1990)

Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units. - Miguel Valero-García; Juan J. Navarro; José J. M. Liabería; Mateo Valero; Tomás Lang (Algorithms and Parallel VLSI Architectures, 1991)

On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. - Jordi Torres; Eduard Ayguadé; Jesús Labarta; José M. Llabería; Mateo Valero (EDMCC, 1991)

Balanced Loop Partitioning Using GTS. - Jesús Labarta; Eduard Ayguadé; Jordi Torres; Mateo Valero; José M. Llabería (LCPC, 1991)

Conflict-Free Strides for Vectors in Matched Memories. - Mateo Valero; Tomás Lang; José María Llabería; Montse Peiron; Juan J. Navarro; Eduard Ayguadé (Parallel Process. Lett., 1991)

Conflict-free access of vectors with power-of-two strides. - Mateo Valero; Tomás Lang; Eduard Ayguadé (ICS, 1992)

Increasing the Number of Strides for Conflict-Free Vector Access. - Mateo Valero; Tomás Lang; José M. Llabería; Montse Peiron; Eduard Ayguadé; Juan J. Navarro (ISCA, 1992)

A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units. - Miguel Valero-García; Juan J. Navarro; José María Llabería; Mateo Valero; Tomás Lang (J. VLSI Signal Process., 1992)

Align and Distribute-based Linear Loop Transformations. - Jordi Torres; Eduard Ayguadé; Jesús Labarta; Mateo Valero (LCPC, 1993)

Access to streams in multiprocessor systems. - Mateo Valero; Montse Peiron; Eduard Ayguadé (PDP, 1993)

Conflict-free access to streams in multiprocessor systems. - Montse Peiron; Mateo Valero; Eduard Ayguadé; Tomás Lang (Microprocess. Microprogramming, 1993)

Chairmen's introduction. - Mateo Valero; Jordi Cortadella; Antonio González 001 (Microprocess. Microprogramming, 1993)

Using Sacks to Organize Registers in VLIW Machines. - Josep Llosa; Mateo Valero; José A. B. Fortes; Eduard Ayguadé (CONPAR, 1994)

Memory Access Synchronization in Vector Multiprocessors. - Mateo Valero; Montse Peiron; Eduard Ayguadé (CONPAR, 1994)

Synchronized access to streams in SIMD vector multiprocessors. - Montse Peiron; Mateo Valero; Eduard Ayguadé (International Conference on Supercomputing, 1994)

Detecting and Using Affinity in an Automatic Data Distribution Tool. - Eduard Ayguadé; Jordi Garcia 001; Mercè Gironés; Jesús Labarta; Jordi Torres; Mateo Valero (LCPC, 1994)

Access To Vectors In Multi-module Memories. - Mateo Valero; Montse Peiron; Eduard Ayguadé (PDP, 1994)

Network Synchronization and Out-of-Order Access to Vectors. - Mateo Valero; Eduard Ayguadé; Montse Peiron (Parallel Process. Lett., 1994)

Automatic generation of loop scheduling for VLIW. - Cristina Barrado; Jesús Labarta; Eduard Ayguadé; Mateo Valero (PACT, 1995)

Non-Consistent Dual Register Files to Reduce Register Pressure. - Josep Llosa; Mateo Valero; Eduard Ayguadé (HPCA, 1995)

A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. - Antonio González 001; Carlos Aliagas; Mateo Valero (International Conference on Supercomputing, 1995)

Vector Multiprocessors with Arbitrated Memory Access. - Montse Peiron; Mateo Valero; Eduard Ayguadé; Tomás Lang (ISCA, 1995)

Hypernode reduction modulo scheduling. - Josep Llosa; Mateo Valero; Eduard Ayguadé; Antonio González 001 (MICRO, 1995)

Quantitative analysis of vector code. - Roger Espasa; Mateo Valero; David A. Padua; Marta Jiménez; Eduard Ayguadé (PDP, 1995)

Analyzing reference patterns in automatic data distribution tools. - Eduard Ayguadé; Jesús Labarta; Jordi Garcia 001; Mercè Gironés; Mateo Valero (Int. J. Parallel Program., 1995)

Conflict-Free Access for Streams in Multimodule Memories. - Mateo Valero; Tomás Lang; Montse Peiron; Eduard Ayguadé (IEEE Trans. Computers, 1995)

Swing module scheduling: a lifetime-sensitive approach. - Josep Llosa; Antonio González 001; Eduard Ayguadé; Mateo Valero (IEEE PACT, 1996)

Decoupled Vector Architectures. - Roger Espasa; Mateo Valero (HPCA, 1996)

Heuristics for Register-Constrained Software Pipelining. - Josep Llosa; Mateo Valero; Eduard Ayguadé (MICRO, 1996)

Loop Parallelization: Revisiting Framework of Unimodular Transformations. - Jordi Torres; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PDP, 1996)

Static Locality Analysis for Cache Management. - F. Jesús Sánchez; Antonio González 001; Mateo Valero (IEEE PACT, 1997)

Effective Usage of Vector Registers in Advanced Vector Architectures. - Luís Villa; Roger Espasa; Mateo Valero (IEEE PACT, 1997)

Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. - Roger Espasa; Mateo Valero (HiPC, 1997)

Virtual registers. - Antonio González 001; Mateo Valero; José González 002; Teresa Monreal Arnal (HiPC, 1997)

Multithreaded Vector Architectures. - Roger Espasa; Mateo Valero (HPCA, 1997)

A Victim Cache for Vector Registers. - Roger Espasa; Mateo Valero (International Conference on Supercomputing, 1997)

Eliminating Cache Conflict Misses through XOR-Based Placement Functions. - Antonio González 001; Mateo Valero; Nigel P. Topham; Joan-Manuel Parcerisa (International Conference on Supercomputing, 1997)

Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. - David López 001; Mateo Valero; Josep Llosa; Eduard Ayguadé (International Conference on Supercomputing, 1997)

Out-of-Order Vector Architectures. - Roger Espasa; Mateo Valero; James E. Smith 001 (MICRO, 1997)

Exploiting instruction- and data-level parallelism. - Roger Espasa; Mateo Valero (IEEE Micro, 1997)

Command Vector Memory Systems: High Performance at Low Cost. - Jesús Corbal; Roger Espasa; Mateo Valero (IEEE PACT, 1998)

Virtual-Physical Registers. - Antonio González 001; José González 002; Mateo Valero (HPCA, 1998)

Vector Architectures: Past, Present and Future. - Roger Espasa; Mateo Valero; James E. Smith 001 (International Conference on Supercomputing, 1998)

Resource Widening Versus Replication: Limits and Performance-cost Trade-off. - David López 001; Josep Llosa; Mateo Valero; Eduard Ayguadé (International Conference on Supercomputing, 1998)

A Performance Study of Out-of-order Vector Architectures and Short Registers. - Luís Villa; Roger Espasa; Mateo Valero (International Conference on Supercomputing, 1998)

Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. - David López 001; Josep Llosa; Mateo Valero; Eduard Ayguadé (MICRO, 1998)

A case for merging the ILP and DLP paradigms. - Francisca Quintana; Roger Espasa; Mateo Valero (PDP, 1998)

Effective usage of vector registers in decoupled vector architectures. - Luís Villa; Roger Espasa; Mateo Valero (PDP, 1998)

An ISA Comparison Between Superscalar and Vector Processors. - Francisca Quintana; Roger Espasa; Mateo Valero (VECPAR, 1998)

Registers Size Influence on Vector Architectures. - Luís Villa; Roger Espasa; Mateo Valero (VECPAR, 1998)

Quantitative Evaluation of Register Pressure on Software Pipelined Loops. - Josep Llosa; Eduard Ayguadé; Mateo Valero (Int. J. Parallel Program., 1998)

Modulo Scheduling with Reduced Register Pressure. - Josep Llosa; Mateo Valero; Eduard Ayguadé; Antonio González 001 (IEEE Trans. Computers, 1998)

Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures. - Daniel Ortega; Ivan Martel; Venkata Krishnan; Eduard Ayguadé; Mateo Valero (IEEE PACT, 1999)

Instruction-Level Parallelism and Uniprocessor Architecture - Introduction. - Pascal Sainrat; Mateo Valero (Euro-Par, 1999)

Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. - David López 001; Josep Llosa; Eduard Ayguadé; Mateo Valero (ICPP, 1999)

Optimization of Instruction Fetch for Decision Support Workloads. - Alex Ramírez; Josep Lluís Larriba-Pey; Carlos Navarro; Xavi Serrano; Mateo Valero; Josep Torrellas (ICPP, 1999)

Increasing effective IPC by exploiting distant parallelism. - Ivan Martel; Daniel Ortega; Eduard Ayguadé; Mateo Valero (International Conference on Supercomputing, 1999)

Adding a vector unit to a superscalar processor. - Francisca Quintana; Jesús Corbal; Roger Espasa; Mateo Valero (International Conference on Supercomputing, 1999)

Software trace cache. - Alex Ramírez; Josep Lluís Larriba-Pey; Carlos Navarro; Josep Torrellas; Mateo Valero (International Conference on Supercomputing, 1999)

Exploiting a New Level of DLP in Multimedia Applications. - Jesús Corbal; Roger Espasa; Mateo Valero (MICRO, 1999)

Delaying Physical Register Allocation through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (MICRO, 1999)

MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. - Jesús Corbal; Roger Espasa; Mateo Valero (SC, 1999)

Enhancing and Exploiting the Locality. - Veljko M. Milutinovic; Mateo Valero (IEEE Trans. Computers, 1999)

A Simulation Study of Decoupled Vector Architectures. - Roger Espasa; Mateo Valero (J. Supercomput., 1999)

The Effect of Code Reordering on Branch Prediction. - Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (IEEE PACT, 2000)

Parallel Computer Architecture. - Silvia M. Müller; Per Stenström; Mateo Valero; Stamatis Vassiliadis (Euro-Par, 2000)

On the Performance of Fetch Engines Running DSS Workloads. - Carlos Navarro; Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (Euro-Par, 2000)

Trace Cache Redundancy: Red & Blue Traces. - Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (HPCA, 2000)

Multiple-banked register file architectures. - José-Lorenzo Cruz; Antonio González 001; Mateo Valero; Nigel P. Topham (ISCA, 2000)

Architectures for One Billion of Transistors. - Mateo Valero (ISSS, 2000)

Two-level hierarchical register file organization for VLIW processors. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (MICRO, 2000)

Improved spill code generation for software pipelined loops. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (PLDI, 2000)

Dynamic Register Renaming Through Virtual-Physical Registers. - Teresa Monreal; Antonio González 001; Mateo Valero; José González 002; Víctor Viñals (J. Instr. Level Parallelism, 2000)

On the Efficiency of Reductions in µ-SIMD Media Extensions. - Jesús Corbal; Roger Espasa; Mateo Valero (IEEE PACT, 2001)

Branch Prediction Using Profile Data. - Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (Euro-Par, 2001)

Topic 15+20: Multimedia and Embedded Systems. - Stamatis Vassiliadis; Francky Catthoor; Mateo Valero; Sorin Cotofana (Euro-Par, 2001)

DLP + TLP Processors for the Next Generation of Media Workloads. - Jesús Corbal; Roger Espasa; Mateo Valero (HPCA, 2001)

On the potential of tolerant region reuse for multimedia applications. - Carlos Álvarez 001; Jesús Corbal; Esther Salamí; Mateo Valero (ICS, 2001)

A novel renaming mechanism that boosts software prefetching. - Daniel Ortega; Mateo Valero; Eduard Ayguadé (ICS, 2001)

Code layout optimizations for transaction processing workloads. - Alex Ramírez; Luiz André Barroso; Kourosh Gharachorloo; Robert S. Cohn; Josep Lluís Larriba-Pey; P. Geoffrey Lowney; Mateo Valero (ISCA, 2001)

MIRS: Modulo Scheduling with Integrated Register Spilling. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (LCPC, 2001)

Modulo scheduling with integrated register spilling for clustered VLIW architectures. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (MICRO, 2001)

Early 21st Century Processors - Guest Editors' Introduction. - Sriram Vajapeyam; Mateo Valero (Computer, 2001)

Instruction fetch architectures and code layout optimizations. - Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (Proc. IEEE, 2001)

Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. - Sandro Bartolini; Roberto Giorgi; Jelica Protic; Cosimo Antonio Prete; Mateo Valero (SIGARCH Comput. Archit. News, 2001)

Lifetime-Sensitive Modulo Scheduling in a Production Environment. - Josep Llosa; Eduard Ayguadé; Antonio González 001; Mateo Valero; Jason Eckhardt (IEEE Trans. Computers, 2001)

Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. - David López 001; Josep Llosa; Mateo Valero; Eduard Ayguadé (IEEE Trans. Computers, 2001)

Cost-Effective Compiler Directed Memory Prefetching and Bypassing. - Daniel Ortega; Eduard Ayguadé; Jean-Loup Baer; Mateo Valero (IEEE PACT, 2002)

Cost effective memory disambiguation for multimedia codes. - Esther Salamí; Jesús Corbal; Carlos Álvarez 001; Mateo Valero (CASES, 2002)

A Comparative Study of Redundancy in Trace Caches (Research Note). - Hans Vandierendonck; Alex Ramírez; Koenraad De Bosschere; Mateo Valero (Euro-Par, 2002)

Hardware Schemes for Early Register Release. - Teresa Monreal; Víctor Viñals; Antonio González 001; Mateo Valero (ICPP, 2002)

Speculative Dynamic Vectorization. - Alex Pajuelo; Antonio González 001; Mateo Valero (ISCA, 2002)

Studying New Ways for Improving Adaptive History Length Branch Predictors. - Ayose Falcón; Oliverio J. Santana; Pedro Medina; Enrique Fernández; Alex Ramírez; Mateo Valero (ISHPC, 2002)

A Comprehensive Analysis of Indirect Branch Prediction. - Oliverio J. Santana; Ayose Falcón; Enrique Fernández; Pedro Medina; Alex Ramírez; Mateo Valero (ISHPC, 2002)

Three-dimensional memory vectorization for high bandwidth media memory systems. - Jesús Corbal; Roger Espasa; Mateo Valero (MICRO, 2002)

Fetching instruction streams. - Alex Ramírez; Oliverio J. Santana; Josep Lluís Larriba-Pey; Mateo Valero (MICRO, 2002)

Initial Results on Fuzzy Floating Point Computation for Multimedia Processors. - Carlos Álvarez 001; Jesús Corbal; Esther Salamí; Mateo Valero (IEEE Comput. Archit. Lett., 2002)

Software Trace Cache for Commercial Applications. - Alex Ramírez; Josep Lluís Larriba-Pey; Carlos Navarro; Mateo Valero; Josep Torrellas (Int. J. Parallel Program., 2002)

Errata on "Measuring Experimental Error in Microprocessor Simulation". - Rajagopalan Desikan; Doug Burger; Stephen W. Keckler; José-Lorenzo Cruz; Fernando Latorre; Antonio González 001; Mateo Valero (SIGARCH Comput. Archit. News, 2002)

A conflict-free memory banking architecture for fast VOQ packet buffers. - Jorge Garcia; Llorenç Cerdà; Jesús Corbal; Mateo Valero (GLOBECOM, 2003)

Hierarchical Clustered Register File Organization for VLIW Processors. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (IPDPS, 2003)

Improving Memory Latency Aware Fetch Policies for SMT Processors. - Francisco J. Cazorla; Enrique Fernández; Alex Ramírez; Mateo Valero (ISHPC, 2003)

Kilo-instruction Processors. - Adrián Cristal; Daniel Ortega; Josep Llosa; Mateo Valero (ISHPC, 2003)

Tolerating Branch Predictor Latency on SMT. - Ayose Falcón; Oliverio J. Santana; Alex Ramírez; Mateo Valero (ISHPC, 2003)

Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (ISHPC, 2003)

A Simple Low-Energy Instruction Wakeup Mechanism. - Marco Antonio Ramírez; Adrián Cristal; Alexander V. Veidenbaum; Luís Villa; Mateo Valero (ISHPC, 2003)

An MPEG-4 performance study for non-SIMD, general purpose architectures. - Sally A. McKee; Zhen Fang 002; Mateo Valero (ISPASS, 2003)

Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. - Jorge García-Vidal; Jesús Corbal; Llorenç Cerdà; Mateo Valero (MICRO, 2003)

A Case for Resource-conscious Out-of-order Processors. - Adrián Cristal; José F. Martínez; Josep Llosa; Mateo Valero (IEEE Comput. Archit. Lett., 2003)

A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. - Francisca Quintana; Jesús Corbal; Roger Espasa; Mateo Valero (Theory Comput. Syst., 2003)

Reducing Fetch Architecture Complexity Using Procedure Inlining. - Oliverio J. Santana; Alex Ramírez; Mateo Valero (Interaction between Compilers and Computer Architectures, 2004)

Predictable performance in SMT processors. - Francisco J. Cazorla; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández; Alex Ramírez; Mateo Valero (Conf. Computing Frontiers, 2004)

A first glance at Kilo-instruction based multiprocessors. - Marco Galluzzi; Valentin Puente; Adrián Cristal; Ramón Beivide; José-Ángel Gregorio; Mateo Valero (Conf. Computing Frontiers, 2004)

Implicit vs. Explicit Resource Allocation in SMT Processors. - Francisco J. Cazorla; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández; Alex Ramírez; Mateo Valero (DSD, 2004)

Feasibility of QoS for SMT. - Francisco J. Cazorla; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández; Alex Ramírez; Mateo Valero (Euro-Par, 2004)

Maintaining Thousands of In-flight Instructions. - Adrián Cristal; Oliverio J. Santana; Mateo Valero (Euro-Par, 2004)

Enabling SMT for real-time embedded systems. - Francisco J. Cazorla; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández; Alex Ramírez; Mateo Valero (EUSIPCO, 2004)

Out-of-Order Commit Processors. - Adrián Cristal; Daniel Ortega; Josep Llosa; Mateo Valero (HPCA, 2004)

A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. - Ayose Falcón; Alex Ramírez; Mateo Valero (HPCA, 2004)

DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. - Francisco J. Cazorla; Alex Ramírez; Mateo Valero; Enrique Fernández (IPDPS, 2004)

Prophet/Critic Hybrid Branch Prediction. - Ayose Falcón; Jared Stark; Alex Ramírez; Konrad Lai; Mateo Valero (ISCA, 2004)

A Content Aware Integer Register File Organization. - Rubén González 001; Adrián Cristal; Daniel Ortega; Alexander V. Veidenbaum; Mateo Valero (ISCA, 2004)

The impact of traffic aggregation on the memory performance of networking applications. - Javier Verdú; Jorge García; Mario Nemirovsky; Mateo Valero (MEDEA@PACT, 2004)

Dynamically Controlled Resource Allocation in SMT Processors. - Francisco J. Cazorla; Alex Ramírez; Mateo Valero; Enrique Fernández (MICRO, 2004)

An Optimized Front-End Physical Register File with Banking and Writeback Filtering. - Miquel Pericàs; Rubén González 001; Adrián Cristal; Alexander V. Veidenbaum; Mateo Valero (PACS, 2004)

Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (SAMOS, 2004)

Initial Evaluation of Multimedia Extensions on VLIW Architectures. - Esther Salamí; Mateo Valero (SAMOS, 2004)

Evaluating kilo-instruction multiprocessors. - Marco Galluzzi; Ramón Beivide; Valentin Puente; José-Ángel Gregorio; Adrián Cristal; Mateo Valero (WMPI, 2004)

Optimising long-latency-load-aware fetch policies for SMT processors. - Francisco J. Cazorla; Alex Ramírez; Mateo Valero; Enrique Fernández (Int. J. High Perform. Comput. Netw., 2004)

Future ILP processors. - Adrián Cristal; Josep Llosa; Mateo Valero; Daniel Ortega (Int. J. High Perform. Comput. Netw., 2004)

A latency-conscious SMT branch prediction architecture. - Ayose Falcón; Oliverio J. Santana; Alex Ramírez; Mateo Valero (Int. J. High Perform. Comput. Netw., 2004)

High-performance and low-power VLIW cores for numerical computations. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. High Perform. Comput. Netw., 2004)

A partitioned instruction queue to reduce instruction wakeup energy. - Marco Antonio Ramírez; Adrián Cristal; Mateo Valero; Alexander V. Veidenbaum; Luís Villa (Int. J. High Perform. Comput. Netw., 2004)

Dynamic Memory Instruction Bypassing. - Daniel Ortega; Mateo Valero; Eduard Ayguadé (Int. J. Parallel Program., 2004)

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (Int. J. Parallel Program., 2004)

QoS for High-Performance SMT Processors in Embedded Systems. - Francisco J. Cazorla; Alex Ramírez; Mateo Valero; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández (IEEE Micro, 2004)

A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. - Adrián Cristal; José F. Martínez; Josep Llosa; Mateo Valero (SIGARCH Comput. Archit. News, 2004)

Toward kilo-instruction processors. - Adrián Cristal; Oliverio J. Santana; Mateo Valero; José F. Martínez (ACM Trans. Archit. Code Optim., 2004)

A low-complexity fetch architecture for high-performance superscalar processors. - Oliverio J. Santana; Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (ACM Trans. Archit. Code Optim., 2004)

Late Allocation and Early Release of Physical Registers. - Teresa Monreal; Víctor Viñals; José González 002; Antonio González 001; Mateo Valero (IEEE Trans. Computers, 2004)

Register Constrained Modulo Scheduling. - Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2004)

Architectural impact of stateful networking applications. - Javier Verdú; Jorge García-Vidal; Mario Nemirovsky; Mateo Valero (ANCS, 2005)

Architectural support for real-time task scheduling in SMT processors. - Francisco J. Cazorla; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández; Alex Ramírez; Mateo Valero (CASES, 2005)

A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. - Marco Antonio Ramírez; Adrián Cristal; Mateo Valero; Alexander V. Veidenbaum; Luís Villa (ICCD, 2005)

A Complexity-Effective Simultaneous Multithreading Architecture. - Carmelo Acosta; Ayose Falcón; Alex Ramírez; Mateo Valero (ICPP, 2005)

A Vector-µSIMD-VLIW Architecture for Multimedia Applications. - Esther Salamí; Mateo Valero (ICPP, 2005)

Implementing Kilo-Instruction Multiprocessors. - Enrique Vallejo 001; Marco Galluzzi; Adrián Cristal; Fernando Vallejo; Ramón Beivide; Per Stenström; James E. Smith 001; Mateo Valero (ICPS, 2005)

An asymmetric clustered processor based on value content. - Rubén González 001; Adrián Cristal; Miquel Pericàs; Mateo Valero; Alexander V. Veidenbaum (ICS, 2005)

Effective Instruction Prefetching via Fetch Prestaging. - Ayose Falcón; Alex Ramírez; Mateo Valero (IPDPS, 2005)

Control-Flow Independence Reuse via Dynamic Vectorization. - Alex Pajuelo; Antonio González 001; Mateo Valero (IPDPS, 2005)

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (ISHPC, 2005)

Decoupled State-Execute Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Alexander V. Veidenbaum; Mateo Valero (ISHPC, 2005)

Multiple Stream Prediction. - Oliverio J. Santana; Alex Ramírez; Mateo Valero (ISHPC, 2005)

Workload Characterization of Stateful Networking Applications. - Javier Verdú; Mario Nemirovsky; Jorge García-Vidal; Mateo Valero (ISHPC, 2005)

Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering. - Raimir Holanda; Javier Verdú; Jorge García-Vidal; Mateo Valero (ISPASS, 2005)

On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. - Friman Sánchez; Mauricio Alvarez 001; Esther Salamí; Alex Ramírez; Mateo Valero (ISPASS, 2005)

Hardware support for early register release. - Teresa Monreal; Víctor Viñals; Antonio González 001; Mateo Valero (Int. J. High Perform. Comput. Netw., 2005)

Kilo-Instruction Processors: Overcoming the Memory Wall. - Adrián Cristal; Oliverio J. Santana; Francisco J. Cazorla; Marco Galluzzi; Tanausú Ramírez; Miquel Pericàs; Mateo Valero (IEEE Micro, 2005)

Better Branch Prediction Through Prophet/Critic Hybrids. - Ayose Falcón; Jared Stark; Alex Ramírez; Konrad K. Lai; Mateo Valero (IEEE Micro, 2005)

Speculative execution for hiding memory latency. - Alex Pajuelo; Antonio González 001; Mateo Valero (SIGARCH Comput. Archit. News, 2005)

The impact of traffic aggregation on the memory performance of networking applications. - Javier Verdú; Jorge García-Vidal; Mario Nemirovsky; Mateo Valero (SIGARCH Comput. Archit. News, 2005)

Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications. - Esther Salamí; Mateo Valero (ACM Trans. Archit. Code Optim., 2005)

Fuzzy Memoization for Floating-Point Multimedia Applications. - Carlos Álvarez 001; Jesús Corbal; Mateo Valero (IEEE Trans. Computers, 2005)

Software Trace Cache. - Alex Ramírez; Josep Lluís Larriba-Pey; Mateo Valero (IEEE Trans. Computers, 2005)

Branch predictor guided instruction decoding. - Oliverio J. Santana; Ayose Falcón; Alex Ramírez; Mateo Valero (PACT, 2006)

Speculative early register release. - Jesús Alastruey; Teresa Monreal; Víctor Viñals; Mateo Valero (Conf. Computing Frontiers, 2006)

Kilo-instruction processors, runahead and prefetching. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Mateo Valero (Conf. Computing Frontiers, 2006)

A decoupled KILO-instruction processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (HPCA, 2006)

Performance Analysis of Sequence Alignment Applications. - Friman Sánchez; Esther Salamí; Alex Ramírez; Mateo Valero (IISWC, 2006)

A simple speculative load control mechanism for energy saving. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Mateo Valero (MEDEA@PACT, 2006)

Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. - Tomer Y. Morad; Uri C. Weiser; A. Kolodnyt; Mateo Valero; Eduard Ayguadé (IEEE Comput. Archit. Lett., 2006)

Predictable Performance in SMT Processors: Synergy between the OS and SMTs. - Francisco J. Cazorla; Peter M. W. Knijnenburg; Rizos Sakellariou; Enrique Fernández; Alex Ramírez; Mateo Valero (IEEE Trans. Computers, 2006)

A DRAM/SRAM Memory Scheme for Fast Packet Buffers. - Jorge García-Vidal; Maribel March; Llorenç Cerdà; Jesús Corbal; Mateo Valero (IEEE Trans. Computers, 2006)

A Flexible Heterogeneous Multi-Core Architecture. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Daniel A. Jiménez; Mateo Valero (PACT, 2007)

Runahead Threads: Reducing Resource Contention in SMT Processors. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Mateo Valero (PACT, 2007)

FAME: FAirly MEasuring Multithreaded Architectures. - Javier Vera; Francisco J. Cazorla; Alex Pajuelo; Oliverio J. Santana; Enrique Fernández; Mateo Valero (PACT, 2007)

Implicit Transactional Memory in Kilo-Instruction Multiprocessors. - Marco Galluzzi; Enrique Vallejo 001; Adrián Cristal; Fernando Vallejo; Ramón Beivide; Per Stenström; James E. Smith 001; Mateo Valero (Asia-Pacific Computer Systems Architecture Conference, 2007)

Hardware Transactional Memory with Operating System Support, HTMOS. - Sasa Tomic; Adrián Cristal; Osman S. Unsal; Mateo Valero (Euro-Par Workshops, 2007)

HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications. - Mauricio Alvarez 001; Esther Salamí; Alex Ramírez; Mateo Valero (IISWC, 2007)

Microarchitectural Support for Speculative Register Renaming. - Jesús Alastruey; Teresa Monreal; Víctor Viñals; Mateo Valero (IPDPS, 2007)

Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. - Mauricio Alvarez 001; Esther Salamí; Alex Ramírez; Mateo Valero (ISPASS, 2007)

Transactional Memory and OpenMP. - Milos Milovanovic; Roger Ferrer; Osman S. Unsal; Adrián Cristal; Xavier Martorell; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IWOMP, 2007)

Multithreaded software transactional memory and OpenMP. - Milos Milovanovic; Roger Ferrer; Vladimir Gajinov; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (MEDEA@PACT, 2007)

On the Problem of Minimizing Workload Execution Time in SMT Processors. - Francisco J. Cazorla; Enrique Fernández; Peter M. W. Knijnenburg; Alex Ramírez; Rizos Sakellariou; Mateo Valero (ICSAMOS, 2007)

Online Prediction of Applications Cache Utility. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (ICSAMOS, 2007)

unreadTVar: Extending Haskell Software Transactional Memory for Performance. - Nehir Sönmez; Cristian Perfumo; Srdjan Stipic; Adrián Cristal; Osman S. Unsal; Mateo Valero (Trends in Functional Programming, 2007)

Explaining Dynamic Cache Partitioning Speed Ups. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (IEEE Comput. Archit. Lett., 2007)

Transactional Memory: An Overview. - Tim Harris 001; Adrián Cristal; Osman S. Unsal; Eduard Ayguadé; Fabrizio Gagliardi; Burton Smith; Mateo Valero (IEEE Micro, 2007)

Energy saving through a simple load control mechanism. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Mateo Valero (SIGARCH Comput. Archit. News, 2007)

Enlarging Instruction Streams. - Oliverio J. Santana; Alex Ramírez; Mateo Valero (IEEE Trans. Computers, 2007)

MultiLayer processing - an execution model for parallel stateful packet processing. - Javier Verdú; Mario Nemirovsky; Mateo Valero (ANCS, 2008)

Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. - Carlos Boneti; Francisco J. Cazorla; Roberto Gioiosa; Mateo Valero (ARCS, 2008)

Evolutionary system for prediction and optimization of hardware architecture performance. - Pedro Ángel Castillo Valdivieso; Juan Julián Merelo Guervós; Miquel Moretó; Francisco J. Cazorla; Mateo Valero; Antonio Miguel Mora; Juan Luis Jiménez Laredo; Sally A. McKee (IEEE Congress on Evolutionary Computation, 2008)

The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. - Cristian Perfumo; Nehir Sönmez; Srdjan Stipic; Osman S. Unsal; Adrián Cristal; Tim Harris 001; Mateo Valero (Conf. Computing Frontiers, 2008)

Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. - Pedro A. Castillo; Antonio Miguel Mora; Juan Julián Merelo Guervós; Juan Luis Jiménez Laredo; Miquel Moretó; Francisco J. Cazorla; Mateo Valero; Sally A. McKee (EvoWorkshops, 2008)

LPA: A First Approach to the Loop Processor Architecture. - Alejandro García; Oliverio J. Santana; Enrique Fernández; Pedro Medina; Mateo Valero (HiPEAC, 2008)

MLP-Aware Dynamic Cache Partitioning. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (HiPEAC, 2008)

Supercomputing for the Future, Supercomputing from the Past (Keynote). - Mateo Valero; Jesús Labarta (HiPEAC, 2008)

Runahead Threads to improve SMT performance. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Mateo Valero (HPCA, 2008)

MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. - Carmelo Acosta; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (ICPP, 2008)

Balancing HPC applications through smart allocation of resources in MT processors. - Carlos Boneti; Roberto Gioiosa; Francisco J. Cazorla; Julita Corbalán; Jesús Labarta; Mateo Valero (IPDPS, 2008)

Software-Controlled Priority Characterization of POWER5 Processor. - Carlos Boneti; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Chen-Yong Cher; Mateo Valero (ISCA, 2008)

A Two-Level Load/Store Queue Based on Execution Locality. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Alexander V. Veidenbaum; Daniel A. Jiménez; Mateo Valero (ISCA, 2008)

WormBench: a configurable workload for evaluating transactional memory systems. - Ferad Zyulkyarov; Adrián Cristal; Sanja Cvijic; Eduard Ayguadé; Mateo Valero; Osman S. Unsal; Tim Harris 001 (MEDEA@PACT, 2008)

A distributed processor state management architecture for large-window processors. - Isidro Gonzalez; Marco Galluzzi; Alexander V. Veidenbaum; Marco Antonio Ramírez; Adrián Cristal; Mateo Valero (MICRO, 2008)

Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. - Sebastián Isaza; Friman Sánchez; Georgi Gaydadjiev; Alex Ramírez; Mateo Valero (SAMOS, 2008)

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. - Jesús Alastruey; Teresa Monreal; Francisco J. Cazorla; Víctor Viñals; Mateo Valero (SBAC-PAD, 2008)

Measuring Operating System Overhead on CMT Processors. - Petar Radojkovic; Vladimir Cakarevic; Javier Verdú; Alejandro Pajuelo; Roberto Gioiosa; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (SBAC-PAD, 2008)

A dynamic scheduler for balancing HPC applications. - Carlos Boneti; Roberto Gioiosa; Francisco J. Cazorla; Mateo Valero (SC, 2008)

Vectorized AES Core for High-throughput Secure Environments. - Miquel Pericàs; Ricardo Chaves; Georgi Gaydadjiev; Stamatis Vassiliadis; Mateo Valero (VECPAR, 2008)

Power-efficient VLIW design using clustering and widening. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. Embed. Syst., 2008)

Nebelung: Execution Environment for Transactional OpenMP. - Milos Milovanovic; Roger Ferrer; Vladimir Gajinov; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (Int. J. Parallel Program., 2008)

Multicore Resource Management. - Kyle J. Nesbit; Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero; James E. Smith 001 (IEEE Micro, 2008)

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (PACT, 2009)

Quantitative analysis of sequence alignment applications on multiprocessor architectures. - Friman Sánchez; Alex Ramírez; Mateo Valero (Conf. Computing Frontiers, 2009)

Oblivious routing schemes in extended generalized Fat Tree networks. - Germán Rodríguez; Cyriel Minkenberg; Ramón Beivide; Ronald P. Luijten; Jesús Labarta; Mateo Valero (CLUSTER, 2009)

Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. - Sutirtha Sanyal; Sourav Roy; Adrián Cristal; Osman S. Unsal; Mateo Valero (HPCC, 2009)

Scalability of Macroblock-level Parallelism for H.264 Decoding. - Mauricio Alvarez-Mesa; Alex Ramírez; Arnaldo Azevedo; Cor Meenderinck; Ben H. H. Juurlink; Mateo Valero (ICPADS, 2009)

Code Semantic-Aware Runahead Threads. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Mateo Valero (ICPP, 2009)

QuakeTM: parallelizing a complex sequential application using transactional memory. - Vladimir Gajinov; Ferad Zyulkyarov; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Tim Harris 001; Mateo Valero (ICS, 2009)

Exploring pattern-aware routing in generalized fat tree networks. - Germán Rodríguez; Ramón Beivide; Cyriel Minkenberg; Jesús Labarta; Mateo Valero (ICS, 2009)

A european perspective on supercomputing. - Mateo Valero (ICS, 2009)

Power-aware load balancing of large scale MPI applications. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero; Alexander V. Veidenbaum (IPDPS, 2009)

Clock gate on abort: Towards energy-efficient hardware Transactional Memory. - Sutirtha Sanyal; Sourav Roy; Adrián Cristal; Osman S. Unsal; Mateo Valero (IPDPS, 2009)

Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. - Nehir Sönmez; Tim Harris 001; Adrián Cristal; Osman S. Unsal; Mateo Valero (IPDPS, 2009)

Hardware support for WCET analysis of hard real-time multicore systems. - Marco Paolieri; Eduardo Quiñones; Francisco J. Cazorla; Guillem Bernat; Mateo Valero (ISCA, 2009)

Characterizing the resource-sharing levels in the UltraSPARC T2 processor. - Vladimir Cakarevic; Petar Radojkovic; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (MICRO, 2009)

EazyHTM: eager-lazy hardware transactional memory. - Sasa Tomic; Cristian Perfumo; Chinmay Eishan Kulkarni; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Tim Harris 001; Mateo Valero (MICRO, 2009)

Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. - Chinmay Eishan Kulkarni; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (PPoPP, 2009)

Atomic quake: using transactional memory in an interactive multiplayer game server. - Ferad Zyulkyarov; Vladimir Gajinov; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Tim Harris 001; Mateo Valero (PPoPP, 2009)

Thread to Core Assignment in SMT On-Chip Multiprocessors. - Carmelo Acosta; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (SBAC-PAD, 2009)

CPU Accounting in CMP Processors. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (IEEE Comput. Archit. Lett., 2009)

An Analyzable Memory Controller for Hard Real-Time CMPs. - Marco Paolieri; Eduardo Quiñones; Francisco J. Cazorla; Mateo Valero (IEEE Embed. Syst. Lett., 2009)

The International Exascale Software Project: a Call To Cooperative Action By the Global High-Performance Community. - Jack J. Dongarra; Peter H. Beckman; Patrick Aerts; Franck Cappello; Thomas Lippert; Satoshi Matsuoka; Paul Messina; Terry Moore; Rick Stevens; Anne E. Trefethen; Mateo Valero (Int. J. High Perform. Comput. Appl., 2009)

BSC Vision Towards Exascale. - Jesús Labarta; Eduard Ayguadé; Mateo Valero (Int. J. High Perform. Comput. Appl., 2009)

Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA. - Mauricio Alvarez 001; Alex Ramírez; Mateo Valero; Arnaldo Azevedo; Cor Meenderinck (Rev. Avances en Sistemas Informática, 2009)

FlexDCP: a QoS framework for CMP architectures. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Rizos Sakellariou; Mateo Valero (ACM SIGOPS Oper. Syst. Rev., 2009)

Available task-level parallelism on the Cell BE. - Alejandro Rico; Alex Ramírez; Mateo Valero (Sci. Program., 2009)

DIA: A Complexity-Effective Decoding Architecture. - Oliverio J. Santana; Ayose Falcón; Alex Ramírez; Mateo Valero (IEEE Trans. Computers, 2009)

Power and thermal characterization of POWER6 system. - Víctor Jiménez; Francisco J. Cazorla; Roberto Gioiosa; Mateo Valero; Carlos Boneti; Eren Kursun; Chen-Yong Cher; Canturk Isci; Alper Buyuktosunoglu; Pradip Bose (PACT, 2010)

Efficient runahead threads. - Tanausú Ramírez; Alex Pajuelo; Oliverio J. Santana; Onur Mutlu; Mateo Valero (PACT, 2010)

Discovering and understanding performance bottlenecks in transactional applications. - Ferad Zyulkyarov; Srdjan Stipic; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (PACT, 2010)

Exploiting Inactive Rename Slots for Detecting Soft Errors. - Mehmet Kayaalp 001; Oguz Ergin; Osman S. Ünsal; Mateo Valero (ARCS, 2010)

Load balancing using dynamic cache allocation. - Miquel Moretó; Francisco J. Cazorla; Rizos Sakellariou; Mateo Valero (Conf. Computing Frontiers, 2010)

Scalability Analysis of Progressive Alignment on a Multicore. - Sebastián Isaza; Friman Sánchez; Georgi Gaydadjiev; Alex Ramírez; Mateo Valero (CISIS, 2010)

Designing OS for HPC Applications: Scheduling. - Roberto Gioiosa; Sally A. McKee; Mateo Valero (CLUSTER, 2010)

A Simulation Framework to Automatically Analyze the Communication-Computation Overlap in Scientific Applications. - Vladimir Subotic; José Carlos Sancho; Jesús Labarta; Mateo Valero (CLUSTER, 2010)

Long DNA Sequence Comparison on Multicore Architectures. - Friman Sánchez; Felipe Cabarcas; Alex Ramírez; Mateo Valero (Euro-Par (2), 2010)

Optimizing job performance under a given power constraint in HPC centers. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero (Green Computing Conference, 2010)

Overlapping communication and computation by using a hybrid MPI/SMPSs approach. - Vladimir Marjanovic; Jesús Labarta; Eduard Ayguadé; Mateo Valero (ICS, 2010)

Power and performance aware reconfigurable cache for CMPs. - Kamil Kedzierski; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (IFMT, 2010)

Comparing last-level cache designs for CMP architectures. - Augusto Vega; Alejandro Rico; Felipe Cabarcas; Alex Ramírez; Mateo Valero (IFMT, 2010)

BSLD threshold driven power management policy for HPC centers. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero (IPDPS Workshops, 2010)

Adapting cache partitioning algorithms to pseudo-LRU replacement policies. - Kamil Kedzierski; Miquel Moretó; Francisco J. Cazorla; Mateo Valero (IPDPS, 2010)

Simulation environment for studying overlap of communication and computation. - Vladimir Subotic; Jesús Labarta; Mateo Valero (ISPASS, 2010)

Task Superscalar: An Out-of-Order Task Pipeline. - Yoav Etsion; Felipe Cabarcas; Alejandro Rico; Alex Ramírez; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (MICRO, 2010)

Architectural Support for Fair Reader-Writer Locking. - Enrique Vallejo 001; Ramón Beivide; Adrián Cristal; Tim Harris 001; Fernando Vallejo; Osman S. Unsal; Mateo Valero (MICRO, 2010)

Effective communication and computation overlap with hybrid MPI/SMPSs. - Vladimir Marjanovic; Jesús Labarta; Eduard Ayguadé; Mateo Valero (PPoPP, 2010)

Thread to strand binding of parallel network applications in massive multi-threaded systems. - Petar Radojkovic; Vladimir Cakarevic; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (PPoPP, 2010)

Debugging programs that use atomic blocks and transactional memory. - Ferad Zyulkyarov; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Mateo Valero (PPoPP, 2010)

Trends and techniques for energy efficient architectures. - Víctor Jiménez; Roberto Gioiosa; Eren Kursun; Francisco J. Cazorla; Chen-Yong Cher; Alper Buyuktosunoglu; Pradip Bose; Mateo Valero (VLSI-SoC, 2010)

Utilization driven power-aware parallel job scheduling. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero (Comput. Sci. Res. Dev., 2010)

Multicore: The View from Europe. - Mateo Valero; Nacho Navarro (IEEE Micro, 2010)

On the Problem of Evaluating the Performance of Multiprogrammed Workloads. - Francisco J. Cazorla; Alex Pajuelo; Oliverio J. Santana; Enrique Fernández; Mateo Valero (IEEE Trans. Computers, 2010)

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. - Adrià Armejach; Azam Seyedi; J. Rubén Titos Gil; Ibrahim Hur; Adrián Cristal; Osman S. Unsal; Mateo Valero (PACT, 2011)

STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems. - Gokcen Kestor; Roberto Gioiosa; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (PACT, 2011)

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory. - Gulay Yalcin; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (PACT, 2011)

From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. - Nehir Sönmez; Oriol Arcas; Gokhan Sayilar; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Satnam Singh; Mateo Valero (ARC, 2011)

Hybrid high-performance low-power and ultra-low energy reliable caches. - Bojan Maric; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (Conf. Computing Frontiers, 2011)

Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications. - Vladimir Subotic; Roger Ferrer; José Carlos Sancho; Jesús Labarta; Mateo Valero (Euro-Par (1), 2011)

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. - Nehir Sönmez; Oriol Arcas; Otto Pflucker; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Satnam Singh; Mateo Valero (FCCM, 2011)

Circuit design of a dual-versioning L1 data cache for optimistic concurrency. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Great Lakes Symposium on VLSI, 2011)

RVC: a mechanism for time-analyzable real-time processors with faulty caches. - Jaume Abella 001; Eduardo Quiñones; Francisco J. Cazorla; Yanos Sazeides; Mateo Valero (HiPEAC, 2011)

FIMSIM: A fault injection infrastructure for microarchitectural simulators. - Gulay Yalcin; Osman S. Unsal; Adrián Cristal; Mateo Valero (ICCD, 2011)

Linear programming based parallel job scheduling for power constrained systems. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero (HPCS, 2011)

RVC-based time-predictable faulty caches for safety-critical systems. - Jaume Abella 001; Eduardo Quiñones; Francisco J. Cazorla; Mateo Valero; Yanos Sazeides (IOLTS, 2011)

A Quantitative Analysis of OS Noise. - Alessandro Morari; Roberto Gioiosa; Robert W. Wisniewski; Francisco J. Cazorla; Mateo Valero (IPDPS, 2011)

Trace-driven simulation of multithreaded applications. - Alejandro Rico; Alejandro Duran; Felipe Cabarcas; Yoav Etsion; Alex Ramírez; Mateo Valero (ISPASS, 2011)

An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures. - Ruken Zilan; Javier Verdú; Jorge García-Vidal; Mario Nemirovsky; Rodolfo A. Milito; Mateo Valero (MASCOTS, 2011)

Hybrid Parallel Programming with MPI/StarSs. - Jesús Labarta; Vladimir Marjanovic; Eduard Ayguadé; Rosa M. Badia; Mateo Valero (PARCO, 2011)

The Impact of Application's Micro-Imbalance on the Communication-Computation Overlap. - Vladimir Subotic; José Carlos Sancho; Jesús Labarta; Mateo Valero (PDP, 2011)

IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. - Marco Paolieri; Eduardo Quiñones; Francisco J. Cazorla; Robert I. Davis 001; Mateo Valero (IEEE Real-Time and Embedded Technology and Applications Symposium, 2011)

Breaking the bandwidth wall in chip multiprocessors. - Augusto Vega; Felipe Cabarcas; Alex Ramírez; Mateo Valero (ICSAMOS, 2011)

Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing. - Sasa Tomic; Adrián Cristal; Osman S. Ünsal; Mateo Valero (SBAC-PAD, 2011)

RMS-TM: a comprehensive benchmark suite for transactional memory systems. - Gokcen Kestor; Vasileios Karakostas; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (ICPE, 2011)

Scalable multicore architectures for long DNA sequence comparison. - Friman Sánchez; Felipe Cabarcas; Alex Ramírez; Mateo Valero (Concurr. Comput. Pract. Exp., 2011)

Characterizing Power and Temperature Behavior of POWER6-Based System. - Víctor Jiménez; Francisco J. Cazorla; Roberto Gioiosa; Mateo Valero; Carlos Boneti; Eren Kursun; Chen-Yong Cher; Canturk Isci; Alper Buyuktosunoglu; Pradip Bose (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

The International Exascale Software Project roadmap. - Jack J. Dongarra; Peter H. Beckman; Terry Moore; Patrick Aerts; Giovanni Aloisio; Jean-Claude Andre; David Barkai; Jean-Yves Berthou; Taisuke Boku; Bertrand Braunschweig; Franck Cappello; Barbara M. Chapman; et al. (Int. J. High Perform. Comput. Appl., 2011)

Hybrid Transactional Memory with Pessimistic Concurrency Control. - Enrique Vallejo 001; Sutirtha Sanyal; Tim Harris 001; Fernando Vallejo; Ramón Beivide; Osman S. Unsal; Adrián Cristal; Mateo Valero (Int. J. Parallel Program., 2011)

Simulating Whole Supercomputer Applications. - Juan Gonzalez; Judit Giménez; Marc Casas; Miquel Moretó; Alex Ramírez; Jesús Labarta; Mateo Valero (IEEE Micro, 2011)

Energy-Aware Accounting and Billing in Large-Scale Computing Facilities. - Víctor Jiménez; Francisco J. Cazorla; Roberto Gioiosa; Eren Kursun; Canturk Isci; Alper Buyuktosunoglu; Pradip Bose; Mateo Valero (IEEE Micro, 2011)

Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems. - Eduardo Quiñones; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (SIGBED Rev., 2011)

RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only). - Gokcen Kestor; Vasileios Karakostas; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (SIGMETRICS Perform. Evaluation Rev., 2011)

A Highly Scalable Parallel Implementation of H.264. - Arnaldo Azevedo; Ben H. H. Juurlink; Cor Meenderinck; Andrei Sergeevich Terechko; Jan Hoogerbrugge; Mauricio Alvarez 001; Alex Ramírez; Mateo Valero (Trans. High Perform. Embed. Archit. Compil., 2011)

Dynamic Cache Partitioning Based on the MLP of Cache Misses. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (Trans. High Perform. Embed. Archit. Compil., 2011)

Assessing Accelerator-Based HPC Reverse Time Migration. - Mauricio Araya-Polo; Javier Cabezas; Mauricio Hanzich; Miquel Pericàs; Félix Rubio; Isaac Gelado; Muhammad Shafiq 003; Enric Morancho; Nacho Navarro; Eduard Ayguadé; José María Cela; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2011)

Optimal task assignment in multithreaded processors: a statistical approach. - Petar Radojkovic; Vladimir Cakarevic; Miquel Moretó; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (ASPLOS, 2012)

TagTM - accelerating STMs with hardware tags for fast meta-data access. - Srdjan Stipic; Sasa Tomic; Ferad Zyulkyarov; Adrián Cristal; Osman S. Ünsal; Mateo Valero (DATE, 2012)

ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. - Bojan Maric; Jaume Abella 001; Mateo Valero (ACM Great Lakes Symposium on VLSI, 2012)

On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks. - Marina García; Enrique Vallejo 001; Ramón Beivide; Miguel Odriozola; Cristobal Camarero; Mateo Valero; Germán Rodríguez; Jesús Labarta; Cyriel Minkenberg (ICPP, 2012)

Enhancing the performance of assisted execution runtime systems through hardware/software techniques. - Gokcen Kestor; Roberto Gioiosa; Osman S. Unsal; Adrián Cristal; Mateo Valero (ICS, 2012)

Evaluating the Impact of TLB Misses on Future HPC Systems. - Alessandro Morari; Roberto Gioiosa; Robert W. Wisniewski; Bryan S. Rosenburg; Todd Inglett; Mateo Valero (IPDPS, 2012)

Improving Cache Management Policies Using Dynamic Reuse Distances. - Nam Duong; Dali Zhao; Taesu Kim; Rosario Cammarota; Mateo Valero; Alexander V. Veidenbaum (MICRO, 2012)

Vector Extensions for Decision Support DBMS Acceleration. - Timothy Hayes 001; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero (MICRO, 2012)

Novel SRAM bias control circuits for a low power L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Mateo Valero (NORCHIP, 2012)

Efficient Sorting on the Tilera Manycore Architecture. - Alessandro Morari; Antonino Tumeo; Oreste Villa; Simone Secchi; Mateo Valero (SBAC-PAD, 2012)

The Network Adapter: The Missing Link between MPI Applications and Network Performance. - Germán Rodríguez; Cyriel Minkenberg; Ronald P. Luijten; Ramón Beivide; Patrick Geoffray; Jesús Labarta; Mateo Valero; Steve Poole 001 (SBAC-PAD, 2012)

Profiling and Optimizing Transactional Memory Applications. - Ferad Zyulkyarov; Srdjan Stipic; Tim Harris 001; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (Int. J. Parallel Program., 2012)

Circuit design of a dual-versioning L1 data cache. - Azam Seyedi; Adrià Armejach; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (Integr., 2012)

Understanding the future of energy-performance trade-off via DVFS in HPC environments. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero (J. Parallel Distributed Comput., 2012)

Resource-bounded multicore emulation using Beefarm. - Oriol Arcas; Nehir Sönmez; Gokhan Sayilar; Satnam Singh; Osman S. Unsal; Adrián Cristal; Ibrahim Hur; Mateo Valero (Microprocess. Microsystems, 2012)

The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications. - Javier Verdú; Alex Pajuelo; Mateo Valero (IEEE Micro, 2012)

Parallel job scheduling for power constrained HPC systems. - Maja Etinski; Julita Corbalán; Jesús Labarta; Mateo Valero (Parallel Comput., 2012)

Hardware transactional memory with software-defined conflicts. - J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Tim Harris 001; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Trans. Archit. Code Optim., 2012)

On the simulation of large-scale architectures using multiple application abstraction levels. - Alejandro Rico; Felipe Cabarcas; Carlos Villavieja; Milan Pavlovic; Augusto Vega; Yoav Etsion; Alex Ramírez; Mateo Valero (ACM Trans. Archit. Code Optim., 2012)

Dynamic Tolerance Region Computing for Multimedia. - Carlos Álvarez 001; Jesús Corbal; Mateo Valero (IEEE Trans. Computers, 2012)

CPU Accounting for Multicore Processors. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (IEEE Trans. Computers, 2012)

APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation. - Bojan Maric; Jaume Abella 001; Mateo Valero (DAC, 2013)

Efficient cache architectures for reliable hybrid voltage operation using EDC codes. - Bojan Maric; Jaume Abella 001; Mateo Valero (DATE, 2013)

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. - Marco Solinas; Rosa M. Badia; François Bodin; Albert Cohen 001; Paraskevas Evripidou; Paolo Faraboschi; Bernhard Fechner; Guang R. Gao; Arne Garbade; Sylvain Girbal; Daniel Goodman 001; Behram Khan; et al. (DSD, 2013)

Global misrouting policies in two-level hierarchical networks. - Marina García; Enrique Vallejo 001; Ramón Beivide; Miguel Odriozola; Cristobal Camarero; Mateo Valero; Jesús Labarta; Germán Rodríguez (INA-OCMC@HiPEAC, 2013)

OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management. - Marina García; Enrique Vallejo 001; Ramón Beivide; Mateo Valero; Germán Rodríguez (Hot Interconnects, 2013)

EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory. - Sasa Tomic; Ege Akpinar; Adrián Cristal; Osman S. Unsal; Mateo Valero (ICCS, 2013)

Efficient Routing Mechanisms for Dragonfly Networks. - Marina García; Enrique Vallejo 001; Ramón Beivide; Miguel Odriozola; Mateo Valero (ICPP, 2013)

HPCS 2013 panel: The era of exascale sciences: Challenges, needs and requirements. - Franck Cappello; Wolfgang Gentzsch; Mateo Valero; Mads Nygård (HPCS, 2013)

HPC System Software for Regular and Irregular Parallel Applications. - Alessandro Morari; Mateo Valero (IPDPS Workshops, 2013)

TM-dietlibc: A TM-aware Real-World System Library. - Vesna Smiljkovic; Martin Nowack; Neboja Miletic; Tim Harris 001; Osman S. Ünsal; Adrián Cristal; Mateo Valero (IPDPS, 2013)

Trace filtering of multithreaded applications for CMP memory simulation. - Alejandro Rico; Alex Ramírez; Mateo Valero (ISPASS, 2013)

On the selection of adder unit in energy efficient vector processing. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISQED, 2013)

Identifying Critical Code Sections in Dataflow Programming Models. - Vladimir Subotic; José Carlos Sancho; Jesús Labarta; Mateo Valero (PDP, 2013)

Killer-mobiles - The Way Towards Energy Efficient High Performance Computers? - Mateo Valero (PECCS, 2013)

Supercomputing with commodity CPUs: are mobile SoCs ready for HPC? - Nikola Rajovic; Paul M. Carpenter; Isaac Gelado; Nikola Puzovic; Alex Ramírez; Mateo Valero (SC, 2013)

Moving from petaflops to petadata. - Michael J. Flynn; Oskar Mencer; Veljko M. Milutinovic; Goran Rakocevic; Per Stenström; Roman Trobec; Mateo Valero (Commun. ACM, 2013)

Programmability and portability for exascale: Top down programming methodology and tools with StarSs. - Vladimir Subotic; Steffen Brinkmann; Vladimir Marjanovic; Rosa M. Badia; José Gracia; Christoph Niethammer; Eduard Ayguadé; Jesús Labarta; Mateo Valero (J. Comput. Sci., 2013)

Hardware support for accurate per-task energy metering in multicore systems. - Qixiao Liu; Miquel Moretó; Víctor Jiménez; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (ACM Trans. Archit. Code Optim., 2013)

Fair CPU time accounting in CMP+SMT processors. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Mateo Valero (ACM Trans. Archit. Code Optim., 2013)

Profile-guided transaction coalescing - lowering transactional overheads by merging transactions. - Srdan Stipic; Vesna Smiljkovic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ACM Trans. Archit. Code Optim., 2013)

SMT Malleability in IBM POWER5 and POWER6 Processors. - Alessandro Morari; Carlos Boneti; Francisco J. Cazorla; Roberto Gioiosa; Chen-Yong Cher; Alper Buyuktosunoglu; Pradip Bose; Mateo Valero (IEEE Trans. Computers, 2013)

Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors. - Petar Radojkovic; Vladimir Cakarevic; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2013)

Stand-Alone Memory Controller for Graphics System. - Tassadaq Hussain; Oscar Palomar; Osman S. Ünsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Amna Haider (ARC, 2014)

PVMC: Programmable Vector Memory Controller. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (ASAP, 2014)

Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster. - Pablo Fuentes 001; José Luis Bosque; Ramón Beivide; Mateo Valero; Cyriel Minkenberg (BDC, 2014)

Dynamic transaction coalescing. - Srdan Stipic; Vasileios Karakostas; Vesna Smiljkovic; Vladimir Gajinov; Osman S. Unsal; Adrián Cristal; Mateo Valero (Conf. Computing Frontiers, 2014)

EVX: Vector execution on low power EDGE cores. - Milovan Duric; Oscar Palomar; Aaron Smith; Osman S. Unsal; Adrián Cristal; Mateo Valero; Doug Burger (DATE, 2014)

DReAM: Per-Task DRAM Energy Metering in Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (Euro-Par, 2014)

APMC: advanced pattern based memory controller (abstract only). - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Santhosh Kumar Rethinagiri (FPGA, 2014)

MAPC: Memory access pattern based controller. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (FPL, 2014)

AMMC: Advanced Multi-Core Memory Controller. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Shakaib A. Gursal (FPT, 2014)

Advanced Pattern based Memory Controller for FPGA based HPC applications. - Tassadaq Hussain; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero (HPCS, 2014)

Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi. - Milan Stanic; Oscar Palomar; Ivan Ratkovic; Milovan Duric; Osman S. Unsal; Adrián Cristal; Mateo Valero (HPCS, 2014)

Author retrospective for software trace cache. - Alex Ramírez; Ayose Falcón; Oliverio J. Santana; Mateo Valero (ICS 25th Anniversary, 2014)

Big Data Processing: Data Flow vs Control Flow (New Benchmarking Methodology). - Anton Kos; Sao Tomac Jakob; Nemanja Trifunovic; Mateo Valero; Veljko Milutinovic (IIKI, 2014)

Scaling Irregular Applications through Data Aggregation and Software Multithreading. - Alessandro Morari; Antonino Tumeo; Daniel G. Chavarría-Miranda; Oreste Villa; Mateo Valero (IPDPS, 2014)

Enabling preemptive multiprogramming on GPUs. - Ivan Tanasic; Isaac Gelado; Javier Cabezas; Alex Ramírez; Nacho Navarro; Mateo Valero (ISCA, 2014)

CODOMs: Protecting software with Code-centric memory Domains. - Lluís Vilanova; Muli Ben-Yehuda; Nacho Navarro; Yoav Etsion; Mateo Valero (ISCA, 2014)

Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISVLSI, 2014)

PAMS: Pattern Aware Memory System for embedded systems. - Tassadaq Hussain; Nehir Sönmez; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Mateo Valero; Shakaib A. Gursal (ReConFig, 2014)

Dynamic-vector execution on a general purpose EDGE chip multiprocessor. - Milovan Duric; Oscar Palomar; Aaron Smith; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero; Doug Burger; Alexander V. Veidenbaum (ICSAMOS, 2014)

DeTrans: Deterministic and Parallel execution of Transactions. - Vesna Smiljkovic; Srdan Stipic; Christof Fetzer; Osman S. Unsal; Adrián Cristal; Mateo Valero (SBAC-PAD, 2014)

Automatic Exploration of Potential Parallelism in Sequential Applications. - Vladimir Subotic; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ISC, 2014)

Per-task Energy Accounting in Computing Systems. - Qixiao Liu; Víctor Jiménez; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (IEEE Comput. Archit. Lett., 2014)

Editorial. - Mateo Valero; Ulises Cortés (Computación y Sistemas, 2014)

Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators. - Sasa Tomic; Adrián Cristal; Osman S. Unsal; Mateo Valero (Int. J. Parallel Program., 2014)

TERAFLUX: Harnessing dataflow in next generation teradevices. - Roberto Giorgi; Rosa M. Badia; François Bodin; Albert Cohen 001; Paraskevas Evripidou; Paolo Faraboschi; Bernhard Fechner; Guang R. Gao; Arne Garbade; Rahulkumar Gayatri; Sylvain Girbal; Daniel Goodman 001; et al. (Microprocess. Microsystems, 2014)

Runtime-Aware Architectures: A First Approach. - Mateo Valero; Miquel Moretó; Marc Casas; Eduard Ayguadé; Jesús Labarta (Supercomput. Front. Innov., 2014)

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation. - Bojan Maric; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (ACM Trans. Design Autom. Electr. Syst., 2014)

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes. - Bojan Maric; Jaume Abella 001; Mateo Valero (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures. - Lluc Alvarez; Miquel Moretó; Marc Casas; Emilio Castillo; Xavier Martorell; Jesús Labarta; Eduard Ayguadé; Mateo Valero (PACT, 2015)

Spark deployment and performance evaluation on the MareNostrum supercomputer. - Rubén Tous; Anastasios Gounaris; Carlos Tripiana; Jordi Torres; Sergi Girona; Eduard Ayguadé; Jesús Labarta; Yolanda Becerra 001; David Carrera 001; Mateo Valero (IEEE BigData, 2015)

Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns. - Pablo Fuentes 001; Enrique Vallejo 001; Cristobal Camarero; Ramón Beivide; Mateo Valero (CLUSTER, 2015)

Runtime-Aware Architectures. - Marc Casas; Miquel Moretó; Lluc Alvarez; Emilio Castillo; Dimitrios Chasapis; Timothy Hayes 001; Luc Jaulmes; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Jesús Labarta; et al. (Euro-Par, 2015)

Hardware Round-Robin Scheduler for Single-ISA Asymmetric Multi-core. - Nikola Markovic; Daniel Nemirovsky; Veljko Milutinovic; Osman S. Unsal; Mateo Valero; Adrián Cristal (Euro-Par, 2015)

VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors. - Timothy Hayes 001; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero (HPCA, 2015)

Increasing multicore system efficiency through intelligent bandwidth shifting. - Víctor Jiménez; Alper Buyuktosunoglu; Pradip Bose; Francis P. O'Connell; Francisco J. Cazorla; Mateo Valero (HPCA, 2015)

Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures. - Kallia Chronaki; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ICS, 2015)

Contention-Based Nonminimal Adaptive Routing in High-Radix Networks. - Pablo Fuentes 001; Enrique Vallejo 001; Marina García; Ramón Beivide; Germán Rodríguez; Cyriel Minkenberg; Mateo Valero (IPDPS, 2015)

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. - Lluc Alvarez; Lluís Vilanova; Miquel Moretó; Marc Casas; Marc González 001; Xavier Martorell; Nacho Navarro; Eduard Ayguadé; Mateo Valero (ISCA, 2015)

Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Milovan Duric; Djordje Peic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISVLSI, 2015)

Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. - Raul Vidal; Marc Casas; Miquel Moretó; Dimitrios Chasapis; Roger Ferrer; Xavier Martorell; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IWOMP, 2015)

Imposing coarse-grained reconfiguration to general purpose processors. - Milovan Duric; Milan Stanic; Ivan Ratkovic; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero; Aaron Smith (SAMOS, 2015)

Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs. - Nikola Markovic; Daniel Nemirovsky; Osman S. Unsal; Mateo Valero; Adrián Cristal (SBAC-PAD, 2015)

Exploiting asynchrony from exact forward recovery for DUE in iterative solvers. - Luc Jaulmes; Marc Casas; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero (SC, 2015)

Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core. - Nikola Markovic; Daniel Nemirovsky; Osman S. Ünsal; Mateo Valero; Adrián Cristal (IEEE Comput. Archit. Lett., 2015)

Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7. - David Prat; Cristobal Ortega; Marc Casas; Miquel Moretó; Mateo Valero (CoRR, 2015)

Picos: A hardware runtime architecture support for OmpSs. - Fahimeh Yazdanpanah; Carlos Álvarez 001; Daniel Jiménez-González; Rosa M. Badia; Mateo Valero (Future Gener. Comput. Syst., 2015)

New Benchmarking Methodology and Programming Model for Big Data Processing. - Anton Kos; Saso Tomazic; Jakob Salom; Nemanja Trifunovic; Mateo Valero; Veljko Milutinovic (Int. J. Distributed Sens. Networks, 2015)

Kernel-to-User-Mode Transition-Aware Hardware Scheduling. - Nikola Markovic; Daniel Nemirovsky; Osman S. Unsal; Mateo Valero; Adrián Cristal (IEEE Micro, 2015)

Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model. - Daniel Nemirovsky; Nikola Markovic; Osman S. Unsal; Mateo Valero; Adrián Cristal (IEEE Micro, 2015)

On-the-fly adaptive routing for dragonfly interconnection networks. - Marina García; Enrique Vallejo 001; Ramón Beivide; Cristobal Camarero; Mateo Valero; Germán Rodríguez; Cyriel Minkenberg (J. Supercomput., 2015)

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling. - Paul Caheny; Marc Casas; Miquel Moretó; Hervé Gloaguen; Maxime Saintes; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PACT, 2016)

POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. - Kallia Chronaki; Miquel Moretó; Marc Casas; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PACT, 2016)

POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core. - Milan Stanic; Oscar Palomar; Timothy Hayes 001; Ivan Ratkovic; Osman S. Unsal; Adrián Cristal; Mateo Valero (PACT, 2016)

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. - Dimitrios Chasapis; Marc Casas; Miquel Moretó; Martin Schulz 001; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ICS, 2016)

CATA: Criticality Aware Task Acceleration for Multicore Processors. - Emilio Castillo; Miquel Moretó; Marc Casas; Lluc Alvarez; Enrique Vallejo 001; Kallia Chronaki; Rosa M. Badia; José Luis Bosque; Ramón Beivide; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IPDPS, 2016)

Future Vector Microprocessor Extensions for Data Aggregations. - Timothy Hayes 001; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISCA, 2016)

A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman S. Unsal; Adrián Cristal; Mateo Valero (ISLPED, 2016)

Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models. - Xubin Tan; Jaume Bosch; Daniel Jiménez-González; Carlos Álvarez-Martínez; Eduard Ayguadé; Mateo Valero (ISPASS, 2016)

Runtime Aware Architectures. - Mateo Valero (PECCS, 2016)

MUSA: a multi-level simulation approach for next-generation HPC machines. - Thomas Grass; César Allande; Adrià Armejach; Alejandro Rico; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas; Miquel Moretó (SC, 2016)

The mont-blanc prototype: an alternative approach for HPC systems. - Nikola Rajovic; Alejandro Rico; Filippo Mantovani; Daniel Ruiz 003; Josep Oriol Vilarrubi; Constantino Gómez; Luna Backes; Diego Nieto; Harald Servat; Xavier Martorell; Jesús Labarta; Eduard Ayguadé; et al. (SC, 2016)

Interconnection Networks in Petascale Computer Systems: A Survey. - Roman Trobec; Radivoje Vasiljevic; Milo Tomasevic; Veljko Milutinovic; Ramón Beivide; Mateo Valero (ACM Comput. Surv., 2016)

Alya: Multiphysics engineering simulation toward exascale. - Mariano Vázquez; Guillaume Houzeaux; Seid Koric; Antoni Artigues; Jazmin Aguado-Sierra; Ruth Aris; Daniel Mira; Hadrien Calmet; Fernando M. Cucchietti; Herbert Coppola-Owen; Ahmed Taha; Evan Dering Burness; et al. (J. Comput. Sci., 2016)

Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System. - Damian Roca; Daniel Nemirovsky; Mario Nemirovsky; Rodolfo A. Milito; Mateo Valero (IEEE Micro, 2016)

PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. - Dimitrios Chasapis; Marc Casas; Miquel Moretó; Raul Vidal; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ACM Trans. Archit. Code Optim., 2016)

Sensible Energy Accounting with Abstract Metering for Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Daniel A. Jiménez; Mateo Valero (ACM Trans. Archit. Code Optim., 2016)

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach. - Petar Radojkovic; Paul M. Carpenter; Miquel Moretó; Vladimir Cakarevic; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (IEEE Trans. Computers, 2016)

Network unfairness in dragonfly topologies. - Pablo Fuentes 001; Enrique Vallejo 001; Cristobal Camarero; Ramón Beivide; Mateo Valero (J. Supercomput., 2016)

DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (ACM Trans. Design Autom. Electr. Syst., 2016)

A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems. - Daniel Nemirovsky; Tugberk Arkose; Nikola Markovic; Mario Nemirovsky; Osman S. Unsal; Adrián Cristal; Mateo Valero (CARLA, 2017)

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals. - Vladimir Dimic; Miquel Moretó; Marc Casas; Mateo Valero (Euro-Par, 2017)

To Distribute or Not to Distribute: The Question of Load Balancing for Performance or Energy. - Esteban Stafford; Borja Pérez; José Luis Bosque; Ramón Beivide; Mateo Valero (Euro-Par, 2017)

Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC. - Lluís Vilanova; Marc Jordà; Nacho Navarro; Yoav Etsion; Mateo Valero (EuroSys, 2017)

Fog Function Virtualization: A flexible solution for IoT applications. - Damian Roca; Josue V. Quiroga; Mateo Valero; Mario Nemirovsky (FMEC, 2017)

Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models. - Xubin Tan; Jaume Bosch; Miquel Vidal; Carlos Álvarez 001; Daniel Jiménez-González; Eduard Ayguadé; Mateo Valero (HPCS, 2017)

ATM: Approximate Task Memoization in the Runtime System. - Iulian Brumar; Marc Casas; Miquel Moretó; Mateo Valero; Gurindar S. Sohi (IPDPS, 2017)

FlexVC: Flexible Virtual Channel Management in Low-Diameter Networks. - Pablo Fuentes 001; Enrique Vallejo 001; Ramón Beivide; Cyriel Minkenberg; Mateo Valero (IPDPS, 2017)

General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models. - Xubin Tan; Jaume Bosch; Miquel Vidal; Carlos Álvarez 001; Daniel Jiménez-González; Eduard Ayguadé; Mateo Valero (IPDPS, 2017)

iQ: An Efficient and Flexible Queue-Based Simulation Framework. - Damian Roca; Daniel Nemirovsky; Marc Casas; Miquel Moretó; Mateo Valero; Mario Nemirovsky (MASCOTS, 2017)

SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (SBAC-PAD, 2017)

A scalable synthetic traffic model of Graph500 for computer networks analysis. - Pablo Fuentes 001; Mariano Benito; Enrique Vallejo 001; José Luis Bosque; Ramón Beivide; Andreea Anghel; Germán Rodríguez; Mitch Gusat; Cyriel Minkenberg; Mateo Valero (Concurr. Comput. Pract. Exp., 2017)

Determinism at Standard-Library Level in TM-Based Applications. - Vesna Smiljkovic; Osman S. Ünsal; Adrián Cristal; Mateo Valero (Int. J. Parallel Program., 2017)

An Integrated Vector-Scalar Design on an In-Order ARM Core. - Milan Stanic; Oscar Palomar; Timothy Hayes 001; Ivan Ratkovic; Adrián Cristal; Osman S. Unsal; Mateo Valero (ACM Trans. Archit. Code Optim., 2017)

Task Scheduling Techniques for Asymmetric Multi-Core Systems. - Kallia Chronaki; Alejandro Rico; Marc Casas; Miquel Moretó; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2017)

Stencil codes on a vector length agnostic architecture. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (PACT, 2018)

Architectural Support for Task Dependence Management with Flexible Software Scheduling. - Emilio Castillo; Lluc Alvarez; Miquel Moretó; Marc Casas; Enrique Vallejo 001; José Luis Bosque; Ramón Beivide; Mateo Valero (HPCA, 2018)

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. - Lluc Alvarez; Marc Casas; Jesús Labarta; Eduard Ayguadé; Mateo Valero; Miquel Moretó (ICS, 2018)

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. - Isaac Sánchez Barrera; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas (ICS, 2018)

Graph partitioning applied to DAG scheduling to reduce NUMA effects. - Isaac Sánchez Barrera; Marc Casas; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PPoPP, 2018)

Runtime-assisted cache coherence deactivation in task parallel programs. - Paul Caheny; Lluc Alvarez; Mateo Valero; Miquel Moretó; Marc Casas (SC, 2018)

Memory Vulnerability: A Case for Delaying Error Reporting. - Luc Jaulmes; Miquel Moretó; Mateo Valero; Marc Casas (CoRR, 2018)

A General Guide to Applying Machine Learning to Computer Architecture. - Daniel Nemirovsky; Tugberk Arkose; Nikola Markovic; Mario Nemirovsky; Osman S. Unsal; Adrián Cristal; Mateo Valero (Supercomput. Front. Innov., 2018)

Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. - Helena Caminal; Diego Caballero; Juan M. Cebrian; Roger Ferrer; Marc Casas; Miquel Moretó; Xavier Martorell; Mateo Valero (J. Supercomput., 2018)

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. - Paul Caheny; Lluc Alvarez; Said Derradji; Mateo Valero; Miquel Moretó; Marc Casas (IEEE Trans. Parallel Distributed Syst., 2018)

Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. - Luc Jaulmes; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas (IEEE Trans. Parallel Distributed Syst., 2018)

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. - Ivan Ratkovic; Oscar Palomar; Milan Stanic; Osman Sabri Unsal; Adrián Cristal; Mateo Valero (IEEE Trans. Very Large Scale Integr. Syst., 2018)

POSTER: An Optimized Predication Execution for SIMD Extensions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (PACT, 2019)

Optimizing computation-communication overlap in asynchronous task-based programs. - Emilio Castillo; Nikhil Jain; Marc Casas; Miquel Moretó; Martin Schulz 001; Ramón Beivide; Mateo Valero; Abhinav Bhatele (ICS, 2019)

Power efficient job scheduling by predicting the impact of processor manufacturing variability. - Dimitrios Chasapis; Miquel Moretó; Martin Schulz 001; Barry Rountree; Mateo Valero; Marc Casas (ICS, 2019)

A Vulnerability Factor for ECC-protected Memory. - Luc Jaulmes; Miquel Moretó; Mateo Valero; Marc Casas (IOLTS, 2019)

Optimizing computation-communication overlap in asynchronous task-based programs: poster. - Emilio Castillo; Nikhil Jain; Marc Casas; Miquel Moretó; Martin Schulz 001; Ramón Beivide; Mateo Valero; Abhinav Bhatele (PPoPP, 2019)

The international race towards Exascale in Europe. - Fabrizio Gagliardi; Miquel Moretó; Mauro Olivieri; Mateo Valero (CCF Trans. High Perform. Comput., 2019)

Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications. - Feng Zhang 007; Jidong Zhai; Marc Snir; Hai Jin 001; Hironori Kasahara; Mateo Valero (Int. J. Parallel Program., 2019)

On the maturity of parallel applications for asymmetric multi-core processors. - Kallia Chronaki; Miquel Moretó; Marc Casas; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Mateo Valero (J. Parallel Distributed Comput., 2019)

A Hardware Runtime for Task-Based Programming Models. - Xubin Tan; Jaume Bosch; Carlos Álvarez 001; Daniel Jiménez-González; Eduard Ayguadé; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2019)

An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (HPCA, 2020)

Improving Accuracy and Speeding Up Document Image Classification Through Parallel Systems. - Javier Ferrando; Juan Luis Domínguez; Jordi Torres; Raúl García; David García; Daniel Garrido; Jordi Cortada; Mateo Valero (ICCS (2), 2020)

RICH: implementing reductions in the cache hierarchy. - Vladimir Dimic; Miquel Moretó; Marc Casas; Jan Ciesko; Mateo Valero (ICS, 2020)

Runtime-guided ECC protection using online estimation of memory vulnerability. - Luc Jaulmes; Miquel Moretó; Mateo Valero; Mattan Erez; Marc Casas (SC, 2020)

The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chips. - Veljko Milutinovic; Milos Kotlar; Ivan Ratkovic; Nenad Korolija; Miljan Djordjevic; Kristy Yoshimoto; Erik Klem; Mateo Valero (CoRR, 2020)

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. - Juan M. Cebrian; Adrián Barredo; Helena Caminal; Miquel Moretó; Marc Casas; Mateo Valero (Future Gener. Comput. Syst., 2020)

Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles. - Damian Roca; Rodolfo A. Milito; Mario Nemirovsky; Mateo Valero (IEEE Intell. Transp. Syst. Mag., 2020)

Using Arm's scalable vector extension on stencil codes. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rubén Langarita; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. - Adrián Barredo; Juan M. Cebrian; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. - Vladimir Dimic; Miquel Moretó; Marc Casas; Mateo Valero (Euro-Par, 2021)

VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations. - Julian Pavon; Iván Vargas Valdivieso; Adrián Barredo; Joan Marimon; Miquel Moretó; Francesc Moll; Osman S. Unsal; Mateo Valero; Adrián Cristal (HPCA, 2021)

The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing. - Veljko M. Milutinovic; Erfan Sadeqi Azer; Kristy Yoshimoto; Gerhard Klimeck; Miljan Djordjevic; Milos Kotlar; Miroslav Bojovic; Bozidar Miladinovic; Nenad Korolija; Stevan Stankovic; Nenad Filipovic; Zoran Babovic; et al. (MECO, 2021)

When Sally Met Harry or When AI Met HPC. - Ulises Cortés; Eduardo Ulises Moya-Sánchez; Mateo Valero (Supercomput. Front. Innov., 2021)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Adaptable Register File Organization for Vector Processors. - Cristóbal Ramírez Lazo; Enrico Reggiani; Carlos Rojas Morales; Roger Figueras Bagué; Luis A. Villa Vargas; Marco Antonio Ramírez Salinas; Mateo Valero Cortés; Osman Sabri Unsal; Adrián Cristal (HPCA, 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing. - Julián Pavón; Iván Vargas Valdivieso; Joan Marimon; Roger Figueras; Francesc Moll; Osman S. Unsal; Mateo Valero; Adrián Cristal (HPCA, 2023)

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications. - Francesco Minervini; Oscar Palomar; Osman S. Unsal; Enrico Reggiani; Josue V. Quiroga; Joan Marimon; Carlos Rojas; Roger Figueras; Abraham Ruiz; Alberto González 004; Jonnatan Mendoza; Iván Vargas; et al. (ACM Trans. Archit. Code Optim., 2023)

QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms. - Julian Pavon; Iván Vargas Valdivieso; Carlos Rojas; César Hernández; Mehmet Aslan; Roger Figueras; Yichao Yuan; Joël Lindegger; Mohammed Alser; Francesc Moll; Santiago Marco-Sola; Oguz Ergin; et al. (ISCA, 2024)