A case study of regenerator placement and regenerator assignment in dynamic translucent elastic optical networks. - Daniel A. R. Chaves; Matheus A. Cavalcante; Helder A. Pereira; Raul C. Almeida (ICTON, 2016)

SimEON: an open-source elastic optical network simulator for academic and industrial purposes. - Matheus A. Cavalcante; Helder A. Pereira; Raul C. Almeida Jr. (Photonic Netw. Commun., 2017)

Optimizing the cost function of power series routing algorithm for transparent elastic optical networks. - Matheus A. Cavalcante; Helder A. Pereira; Daniel A. R. Chaves; Raul C. Almeida Jr. (Opt. Switch. Netw., 2018)

Evolutionary Multiobjective Strategy for Regenerator Placement in Elastic Optical Networks. - Matheus A. Cavalcante; Helder A. Pereira; Daniel A. R. Chaves; Raul C. Almeida Jr. (IEEE Trans. Commun., 2018)

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. - Matheus A. Cavalcante; Fabian Schuiki; Florian Zaruba; Michael Schaffner; Luca Benini (CoRR, 2019)

Design of an open-source bridge between non-coherent burst-based and coherent cache-line-based memory systems. - Matheus A. Cavalcante; Andreas Kurth; Fabian Schuiki; Luca Benini (CF, 2020)

Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. - Matheus A. Cavalcante; Fabian Schuiki; Florian Zaruba; Michael Schaffner; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2020)

MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. - Matheus A. Cavalcante; Samuel Riedel; Antonio Pullini; Luca Benini (DATE, 2021)

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. - Matteo Perotti; Matheus A. Cavalcante; Nils Wistoff; Renzo Andri; Lukas Cavigelli; Luca Benini (ASAP, 2022)

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. - Matheus A. Cavalcante; Anthony Agnesina; Samuel Riedel; Moritz Brunion; Alberto García-Ortiz; Dragomir Milojevic; Francky Catthoor; Sung Kyu Lim; Luca Benini (DATE, 2022)

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. - Matheus A. Cavalcante; Domenic Wüthrich; Matteo Perotti; Samuel Riedel; Luca Benini (ICCAD, 2022)

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. - Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (ISLPED, 2022)

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. - Gianna Paulin; Matheus A. Cavalcante; Paul Scheffler; Luca Bertaccini; Yichao Zhang 003; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. - Andreas Kurth; Wolfgang Rönninger; Thomas Benz; Matheus A. Cavalcante; Fabian Schuiki; Florian Zaruba; Luca Benini (IEEE Trans. Computers, 2022)

Sparse Hamming Graph: A Customizable Network-on-Chip Topology. - Patrick Iff; Maciej Besta; Matheus A. Cavalcante; Tim Fischer 001; Luca Benini; Torsten Hoefler (DAC, 2023)

HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement. - Patrick Iff; Maciej Besta; Matheus A. Cavalcante; Tim Fischer 001; Luca Benini; Torsten Hoefler (DAC, 2023)

PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. - Vikram Jain; Matheus A. Cavalcante; Nazareno Bruschi; Michael Rogenmoser; Thomas Benz; Andreas Kurth; Davide Rossi; Luca Benini; Marian Verhelst (DAC, 2023)

MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. - Samuel Riedel; Gua Hao Khov; Sergio Mazzola; Matheus A. Cavalcante; Renzo Andri; Luca Benini (DATE, 2023)

MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. - Samuel Riedel; Matheus A. Cavalcante; Manos Frouzakis; Domenic Wüthrich; Enis Mustafa; Arlind Billa; Luca Benini (ICECS, 2023)

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. - MohammadHossein AskariHemmat; Théo Dupuis; Yoan Fournier; Nizar El Zarif; Matheus A. Cavalcante; Matteo Perotti; Frank K. Gürkaynak; Luca Benini; François Leduc-Primeau; Yvon Savaria; Jean-Pierre David (ISCAS, 2023)

FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. - Tim Fischer 001; Michael Rogenmoser; Matheus A. Cavalcante; Frank K. Gürkaynak; Luca Benini (CoRR, 2023)

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. - Matteo Perotti; Matheus A. Cavalcante; Renzo Andri; Lukas Cavigelli; Luca Benini (CoRR, 2023)

Fighting back the von Neumann bottleneck with small- and large-scale vector microprocessors. - Matheus A. Cavalcante (Hartung-Gorre Verlag, 2023)

Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. - Matteo Perotti; Matheus A. Cavalcante; Alessandro Ottaviano; Jiantao Liu; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. - Tim Fischer 001; Michael Rogenmoser; Matheus A. Cavalcante; Frank K. Gürkaynak; Luca Benini (IEEE Des. Test, 2023)

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. - Samuel Riedel; Matheus A. Cavalcante; Renzo Andri; Luca Benini (IEEE Trans. Computers, 2023)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. - Matteo Perotti; Michele Raeber; Mattia Sinigaglia; Matheus A. Cavalcante; Davide Rossi; Luca Benini (ASAP, 2024)

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. - Matteo Perotti; Yichao Zhang 003; Matheus A. Cavalcante; Enis Mustafa; Luca Benini (DATE, 2024)

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. - Yichao Zhang 003; Marco Bertuletti; Samuel Riedel; Matheus A. Cavalcante; Alessandro Vanelli-Coralli; Luca Benini (ACM Great Lakes Symposium on VLSI, 2024)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products. - Luca Bertaccini; Gianna Paulin; Matheus A. Cavalcante; Tim Fischer 001; Stefan Mach; Luca Benini (IEEE Trans. Emerg. Top. Comput., 2024)

Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. - Matteo Perotti; Matheus A. Cavalcante; Renzo Andri; Lukas Cavigelli; Luca Benini (IEEE Trans. Computers, 2024)

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. - Nesara Eranna Bethur; Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. - Matteo Perotti; Samuel Riedel; Matheus A. Cavalcante; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)